A 30 MHz DDS clock generator with 8-bit, 130 ps delay generator and-50 dBc spurious level

European Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 401-404

  Heiskanen, A ^a   Mantyniemi, A ^a   Rahkonen, T ^a  

^a UNIVERSITY OF OULU   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK GENERATOR; CLOCK GENERATOR CIRCUIT; PROGRAMMABLE DELAY GENERATORS; RECONSTRUCTION FILTERS; SAMPLING FREQUENCIES; SPURIOUS LEVELS; SPURIOUS SIGNALS; SQUARE-WAVE CLOCKS;

CMOS INTEGRATED CIRCUITS;

ELECTRIC CLOCKS;

EID: 84893655983     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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