An analogue delay line for virtual clock enhancement in DDS

European Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 476-479

  Richter, R ^a   Jentschel, H J ^a  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CONVENTIONAL APPROACH; DELAY-LOCKED LOOPS; DIGITAL SIGNAL PROCESSING (DSP); DIRECT DIGITAL SYNTHESIS; FREQUENCY GENERATION; GENERATED FREQUENCY; PHASE ACCUMULATORS; SPECTRAL PERFORMANCE;

CLOCKS; DIRECT DIGITAL CONTROL SYSTEMS; SIGNAL PROCESSING;

WAVES;

EID: 84888056803     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. V. F. Kroupa, "Direct Digital Frequency Synthesizers", IEEE Press, 1998
2. R. Richter, "Ein Beitrag zur Modellierung der Direkten Digitalen F requenzsynthese", Dissertation, TU Dresden, 1999
3. R. Richter, H. Garbe, H.-J. Jentschel: "Direct Digital Synthesis IC-Design and Implementation", DATE99, Munich, 1999