Concurrent fault detection in a hardware implementation of the RC5 encryption algorithm

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn 2003-January, Issue , 2003, Pages 423-432

  Bertoni, Guido ^a   Breveglieri, Luca ^a   Koren, Israel ^b   Maistri, Paolo ^a   Piuri, Vincenzo ^c  

^a POLITECNICO DI MILANO   (Italy)

^b University of Massachusetts   (United States)

^c UNIVERSITY OF MILAN   (Italy)

Author keywords

Cryptography; error detecting codes; fault detection; RC5; VLSI architecture

Indexed keywords

ALGORITHMS; CODES (SYMBOLS); COMPUTER ARCHITECTURE; COSTS; CRYPTOGRAPHY; ERROR DETECTION; ERRORS; FAILURE ANALYSIS; FAULT TOLERANCE; HARDWARE; HARDWARE SECURITY;

BLOCK CIPHER ALGORITHMS; CRYPTOGRAPHIC ALGORITHMS; ERROR DETECTING CODES; FAULT DIAGNOSIS AND TOLERANCES; HARDWARE IMPLEMENTATIONS; RC5; SOFTWARE AND HARDWARES; VLSI ARCHITECTURES;

FAULT DETECTION;

EID: 84893543356     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2003.1212865     Document Type: Conference Paper

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