A parity code based fault detection for an implementation of the Advanced Encryption Standard

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2002-January, Issue , 2002, Pages 51-59

  Bertoni, G ^a   Breveglieri, L ^a   Koren, I ^b   Maistri, P ^a   Piuri, V ^c  

^a POLITECNICO DI MILANO   (Italy)

^b University of Massachusetts   (United States)

^c UNIVERSITY OF MILAN   (Italy)

Author keywords

Circuit faults; Code standards; Costs; Cryptography; Electrical fault detection; Fault detection; Hardware; Information technology; Partitioning algorithms; Scheduling

Indexed keywords

CODES (SYMBOLS); COMPUTER HARDWARE; COST BENEFIT ANALYSIS; COSTS; CRYPTOGRAPHY; DATA PRIVACY; DEFECTS; ELECTRIC FAULT LOCATION; FAULT TOLERANCE; HARDWARE; INFORMATION TECHNOLOGY; SCHEDULING; SCHEDULING ALGORITHMS;

ADVANCED ENCRYPTION STANDARD; CIRCUIT FAULTS; ELECTRICAL FAULT DETECTIONS; ENCRYPTION/DECRYPTION; ENCRYPTION/DECRYPTION PROCESS; FAULT DETECTION SCHEMES; HARDWARE IMPLEMENTATIONS; PARTITIONING ALGORITHMS;

FAULT DETECTION;

EID: 0037542974     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.2002.1173501     Document Type: Conference Paper

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