A formal verification framework for Bluespec System Verilog

Forum on Specification and Design Languages

Volumn , Issue , 2013, Pages

  Ouchani, Samir ^a   Mohamed, Otmane Ait ^a   Debbabi, Mourad ^a  

^a Dept of Electrical and Computer Engineering   (Canada)

Author keywords

BlueSpec System Verilog; PCTL; PRISM Model Checker; SysML Activity Diagram

Indexed keywords

FORMAL VERIFICATIONS; HARDWARE DESIGN; HARDWARE SYNTHESIS; MODEL CHECKER; PCTL; SYMBOLIC MODEL CHECKERS; SYSML ACTIVITY DIAGRAMS; SYSTEM VERILOG;

ALGORITHMS; DESIGN; HARDWARE; MODEL CHECKING; PRISMS; SPECIFICATIONS; SYSTEMS ANALYSIS;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 84891330571     PISSN: 16369874     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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