메뉴 건너뛰기




Volumn , Issue , 2012, Pages 4670-4675

A tool to support Bluespec SystemVerilog coding based on UML diagrams

Author keywords

[No Author keywords available]

Indexed keywords

CODE GENERATION; DEVELOPMENT TIME; GENERATION PROCESS; HARDWARE AND SOFTWARE; HIGH-LEVEL MODELS; SYSTEMVERILOG; TARGET LANGUAGE; UML DIAGRAMS;

EID: 84872914766     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IECON.2012.6389493     Document Type: Conference Paper
Times cited : (13)

References (21)
  • 1
    • 70350703466 scopus 로고    scopus 로고
    • Guest editors' introduction: The true state of the art of ESL design
    • IEEE, May
    • S. Shukla, C. Pixley, and G. Smith, "Guest Editors' Introduction: The True State of the Art of ESL Design," Design Test of Computers, IEEE, vol. 23, no. 5, pp. 335 - 337, May 2006.
    • (2006) Design Test of Computers , vol.23 , Issue.5 , pp. 335-337
    • Shukla, S.1    Pixley, C.2    Smith, G.3
  • 2
    • 33947101971 scopus 로고    scopus 로고
    • A platform-based taxonomy for ESL design
    • IEEE, May
    • D. Densmore and R. Passerone, "A Platform-Based Taxonomy for ESL Design," Design Test of Computers, IEEE, vol. 23, no. 5, pp. 359 -374, May 2006.
    • (2006) Design Test of Computers , vol.23 , Issue.5 , pp. 359-374
    • Densmore, D.1    Passerone, R.2
  • 5
    • 51349164963 scopus 로고    scopus 로고
    • A model-driven development approach to mapping UML state diagrams to synthesizable VHDL
    • Oct.
    • S. Wood, D. Akehurst, O. Uzenkov, W. Howells, and K. McDonald-Maier, "A Model-Driven Development Approach to Mapping UML State Diagrams to Synthesizable VHDL," Computers, IEEE Transactions on, vol. 57, no. 10, pp. 1357 -1371, Oct. 2008 .
    • (2008) Computers, IEEE Transactions on , vol.57 , Issue.10 , pp. 1357-1371
    • Wood, S.1    Akehurst, D.2    Uzenkov, O.3    Howells, W.4    McDonald-Maier, K.5
  • 10
    • 84872905336 scopus 로고    scopus 로고
    • Aldec, Inc. (2011) Active-HDL. [Online]. Available: http://www.aldec.com/ en/products/fpga-simulation/active-hdl/
    • (2011) Active-HDL
  • 11
    • 84872907660 scopus 로고    scopus 로고
    • Mentor Graphics Corporation. (2006) HDL Designer. [Online]. Available: http://www.mentor.com/products/fpga/hdl-design/hdl-designer-series/
    • (2006) HDL Designer
  • 12
    • 84872941510 scopus 로고    scopus 로고
    • HDL Works. (2011) EASE Graphical HDL Entry. [Online]. Available: http://www.hdlworks.com/products/ease/index.html/
    • (2011) EASE Graphical HDL Entry
  • 14
    • 84872954419 scopus 로고    scopus 로고
    • University of Mannheim - Computer Architecture Group (Jul)
    • University of Mannheim - Computer Architecture Group. (2010, Jul.) FSMDesigner4 - A high-level design entry tool. [Online]. Available: http://sourceforge.net/projects/fsmdesigner/
    • (2010) FSMDesigner4 - A High-level Design Entry Tool
  • 15
    • 84872940464 scopus 로고    scopus 로고
    • [Online; acessado em 10-Outubro-2010]
    • Bluespec Inc, "The Synthesizable Modeling Company," http://www.bluespec.com/. 2010, [Online; acessado em 10-Outubro-2010].
    • (2010) The Synthesizable Modeling Company
  • 19
    • 84872916707 scopus 로고    scopus 로고
    • No Magic, Inc. (Feb.)
    • No Magic, Inc. (2012, Feb.) MagicDraw. [Online]. Available: https://www.magicdraw.com/
    • (2012)
  • 21
    • 84872960343 scopus 로고    scopus 로고
    • Nov.
    • Apache Software Foundation. (2010, Nov.) The Apache Velocity Project. [Online]. Available: http://velocity.apache.org/
    • (2010) He Apache Velocity Project


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.