SCOPUS 정보 검색 플랫폼

Proceedings of the VLDB Endowment

Volumn 6, Issue 12, 2013, Pages 1290-1293

Eagletree: Exploring the design space of SSD-based algorithms

(5) Dayan, Niv a Svendsen, Martin Kjær a Bjørling, Matias a Bonnet, Philippe a Bouganim, Luc b,c

a IT UNIVERSITY OF COPENHAGEN (Denmark)

b INRIA (France)

c LABORATOIRE DES SCIENCES DU CLIMAT ET DE L ENVIRONNEMENT (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPLEX DESIGNS; EXPERIMENTAL METHODOLOGY; INTRINSIC PARALLELISMS; MOVING TARGETS; PERFORMANCE CHARACTERISTICS; SIMULATION FRAMEWORK; SOLID STATE DRIVES; SYSTEM DESIGNERS;

TREES (MATHEMATICS);

EID: 84891053124 PISSN: None EISSN: 21508097 Source Type: Journal
DOI: 10.14778/2536274.2536298 Document Type: Article

Times cited : (23)

References (10)

1
- 84991957861
- Design tradeoffs for SSD performance
- N.Agrawal, V.Prabhakaran, T.Wobber, John.Davis, M.Manasse, R.Panigrahy. Design tradeoffs for SSD performance. USENIX ATC, 2008
- (2008) USENIX ATC
- Agrawal, N.¹ Prabhakaran, V.² Wobber, T.³ Davis, J.⁴ Manasse, M.⁵ Panigrahy, R.⁶

2
- 85084015236
- The Necessary Death of the Block Device Interface
- M.Bjørling, P.Bonnet, L.Bouganim, N.Dayan. The Necessary Death of the Block Device Interface. CIDR, 2013.
- (2013) CIDR
- Bjørling, M.¹ Bonnet, P.² Bouganim, L.³ Dayan, N.⁴

3
- 84863765688
- System Co-Design and Data Management for Flash Devices
- P. Bonnet, L. Bouganim, I. Koltsidas, S. Viglas. System Co-Design and Data Management for Flash Devices. VLDB 2011.
- (2011) VLDB
- Bonnet, P.¹ Bouganim, L.² Koltsidas, I.³ Viglas, S.⁴

4
- 84858651045
- uFLIP: Understanding flash I/O patterns
- L. Bouganim, B. T. Jònsson, and P. Bonnet. uFLIP: Understanding flash I/O patterns. CIDR, 2009.
- (2009) CIDR
- Bouganim, L.¹ Jònsson, B.T.² Bonnet, P.³

5
- 67650065541
- DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings
- A. Gupta, Y. Kim, and B. Urgaonkar. DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings. In ASPLOS, 2009.
- (2009) In ASPLOS
- Gupta, A.¹ Kim, Y.² Urgaonkar, B.³

6
- 84866183389
- NANDFlashSim: Intrinsic latency variation aware NAND flash memory system modeling and simulation at microarchitecture level
- M.Jung, E.Wilson, D.Donofrio, J.Shalf, M.Kandemir. NANDFlashSim: Intrinsic latency variation aware NAND flash memory system modeling and simulation at microarchitecture level. MSST 2012
- (2012) MSST
- Jung, M.¹ Wilson, E.² Donofrio, D.³ Shalf, J.⁴ Kandemir, M.⁵

7
- 74349083686
- FlashSim: A Simulator for NAND Flash-based Solid-State Drives
- Y.Kim, B.Tauras, A.Gupta, D.Mihai, N.Urgaonkar. FlashSim: A Simulator for NAND Flash-based Solid-State Drives. SIMUL, 2009
- (2009) SIMUL
- Kim, Y.¹ Tauras, B.² Gupta, A.³ Mihai, D.⁴ Urgaonkar, N.⁵

8
- 79960920699
- Hot Data Identification for Flash-based Storage Systems Using Multiple Bloom Filters
- D.Park, D.Du. Hot Data Identification for Flash-based Storage Systems Using Multiple Bloom Filters. MSST, 2011
- (2011) MSST
- Park, D.¹ Du, D.²

9
- 84997309669
- Getting Real: Lessons in Transitioning Research Simulations into Hardware Systems
- M. Saxena, Y. Zhang, M. M. Swift, A. C. Arpaci-Dusseau, R. H. Arpaci-Dusseau. Getting Real: Lessons in Transitioning Research Simulations into Hardware Systems, FAST, 2013.
- (2013) FAST
- Saxena, M.¹ Zhang, Y.² Swift, M.M.³ Arpaci-Dusseau, A.C.⁴ Arpaci-Dusseau, R.H.⁵

10
- 84872109857
- The OpenSSD Project. http://www.openssd-project.org
- The OpenSSD Project

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.