A Complete 10 gbps Chip-to-chip digital CMOS silicon photonic link

CLEO: Applications and Technology, CLEO_AT 2012

Volumn , Issue , 2012, Pages

  Zheng, Xuezhe ^a   Luo, Ying ^a   Lexau, Jon ^a   Liu, Frankie ^a   Li, Guoliang ^a   Thacker, Hiren ^a   Shubin, Ivan ^a   Yao, Jin ^a   Ho, Ron ^a   Cunningham, John E ^a   Krishnamoorthy, Ashok V ^a  

^a ORACLE CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS;

10 GBPS; CHIP TO CHIPS; DIGITAL CMOS; OPTICAL POWER; POWER SUPPLY; RETIMING;

SILICON PHOTONICS;

EID: 84890691603     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1364/cleo_at.2012.cth5d.6     Document Type: Conference Paper

References (8)

1. A.V. Krishnamoorthy et al., "Computer systems based on silicon photonic interconnects," Proceedings IEEE 97(7), 1337-1361 (2009).
2. Supercomputing '05 demo in Fiber Optics and Communications, ed. H. Pan and P. Polishuk, IGI group, Dec. 2006, pp. 10-11
3. A. Narasimha et al., "A fully integrated 4x10Gb/s DWDM transceiver in standard 0.13um CMOS SOI," IEEE ISSCC 2007, pp. 42-43.
4. A. Alduino, et al., "Integrated Photonics Research, Silicon and Nanophotonics," OSA Technical Digest (CD), paper PDIWI5, 2010.
5. G. Li et al., "Ultralow-power, high-performance Si photonic transmitter," OFC, OMI2, pp.1-3, 2010.
6. J.E. Cunningham et al., "Integration and packaging of a macrochip with silicon nanophotonic links," IEEE JSTQE 17(3), pp.546-558, 2011.
7. X. Zheng et al., "Ultra-Low Power Arrayed CMOS Silicon Photonic Transceivers for an 80 Gbps WDM Optical Link," OFC/NFOEC 2011, PDPA1, 2011.
8. F. Liu et al., "10 Gbps, 535 fJ/b optical transceiver circuits in 40 nm CMOS," IEEE Symposium on VLSI Circuits, C27-3, 2011.