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Volumn Part F129250, Issue , 1998, Pages 23-28

Issues in embedded DRAM development and applications

Author keywords

[No Author keywords available]

Indexed keywords

COMMERCE;

EID: 77955637045     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/isss.1998.730592     Document Type: Conference Paper
Times cited : (8)

References (18)
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  • 5
  • 8
    • 0031145559 scopus 로고    scopus 로고
    • Modular Architecture for a 6.4-Gbyte/s, 8-Mbit DRAM-integrated media chip
    • May
    • T. Watanabe et al. Modular Architecture for a 6.4-Gbyte/s, 8-Mbit DRAM-integrated media chip. IEEE Journal of Solid-State Circuits, Vol. 32, pp. 635-641, May 1997.
    • (1997) IEEE Journal of Solid-State Circuits , vol.32 , pp. 635-641
    • Watanabe, T.1
  • 9
    • 0031706865 scopus 로고    scopus 로고
    • A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator
    • February
    • T. Yabe et al. A Configurable DRAM Macro Design for 2112 Derivative Organizations to be synthesized Using a Memory Generator. In 1998 International Solid State Circuits Conference, Digest of Technical Papers, pages 72-73, February 1998.
    • (1998) 1998 International Solid State Circuits Conference, Digest of Technical Papers , pp. 72-73
    • Yabe, T.1
  • 10
    • 0032072126 scopus 로고    scopus 로고
    • An access- sequence control scheme to enhance random-Access per-formance of embedded DRAMs
    • May
    • K. Ayukawa, T. Watanabe, and S. Narita. An Access- Sequence Control Scheme to Enhance Random-Access Performance of Embedded DRAMs. IEEE Journal of Solid- State Circuits, Vol. 33, No. 5, pp.800-806, May 1998.
    • (1998) IEEE Journal of Solid- State Circuits , vol.33 , Issue.5 , pp. 800-806
    • Ayukawa, K.1    Watanabe, T.2    Narita, S.3
  • 11
    • 84893800156 scopus 로고    scopus 로고
    • Energy-delay efficient data storage and transfer architectures: Circuit technology versus design methodology solutions
    • February
    • F. Catthoor. Energy-delay efficient data storage and transfer architectures: circuit technology versus design methodology solutions. In Design, Automation and Test in Europe, pages 709-714, February 1998.
    • (1998) Design, Automation and Test in Europe , pp. 709-714
    • Catthoor, F.1
  • 13
    • 0031073176 scopus 로고    scopus 로고
    • Intelligent RAM (IRAM): Chips that remember and compute
    • Digest of Technical Papers, February
    • D. Patterson et al. Intelligent RAM (IRAM): Chips that Remember and Compute. In 1997 International Solid State Circuits Conference, Digest of Technical Papers, volume 40, pages 224-225, February 1997.
    • (1997) 1997 International Solid State Circuits Conference , vol.40 , pp. 224-225
    • Patterson, D.1
  • 14
    • 0030081181 scopus 로고    scopus 로고
    • A multimedia 32b RISC microprocessor with 16 Mb DRAM
    • Digest of Technical Papers, February
    • T. Shimizu et al. A Multimedia 32b RISC Microprocessor with 16 Mb DRAM. In 1996 International Solid State Circuits Conference, Digest of Technical Papers, volume 39, pages 216-217, February 1996.
    • (1996) 1996 International Solid State Circuits Conference , vol.39 , pp. 216-217
    • Shimizu, T.1
  • 15
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    • A 7.68-GIPS 3.84-Gb/s 1-W parallel image-processing RAM integrating a 16Mb DRAM and 128 processors
    • February
    • Y. Aiomoto et al. A 7.68-GIPS 3.84-GB/s 1-W Parallel Image-Processing RAM integrating a 16Mb DRAM and 128 processors. In 1996 International Solid State Circuits Conference, Digest of Technical Papers, pages 372-373, February 1996.
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    • Aiomoto, Y.1
  • 16
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    • K. Murakami, S. Shirakawa, and H. Miyajima. Parallel Processing RAM Chip with 256Mb DRAM and Quad Processors. In 1997 International Solid State Circuits Conference, Digest of Technical Papers, volume 40, pages 228229, February 1997.
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  • 17
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.