On mismatch errors in analog-VLSI error correcting decoders

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 4, Issue , 2001, Pages 198-201

  Lustenberger, Felix ^a   Loeliger, Hans Andrea ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG DECODERS; ANALYTICAL RESULTS; ERROR CORRECTING CODE; ERROR-CORRECTING; MISMATCH ERRORS; NON-IDEALITIES; PERFORMANCE DEGRADATION; TRANSISTOR MISMATCH;

TURBO CODES;

VLSI CIRCUITS;

EID: 84888032339     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922206     Document Type: Conference Paper

References (19)

1. C. Berrou, A. Glavieux and P. Thitimajshima. "Near Shannon-limit error-correcting coding and decoding: turbo codes". In Proc. ICC, pp. 1064-1070. Geneva. May 1993.
2. R. G. Gallager. Low-Density Parity-Check Codes. MIT Press, 1963.
3. D. J. C. MacKay. "Good error-correcting codes based on very sparse matrices". IEEE Trans. Inf. Theory, vol. 45, no. 2, pp. 399-431, March 1999.
4. F. R. Kschischang, B. J. Frey, and H.-A. Loeliger. "Factor graphs and the sum-product algorithm", June 2000. To appear in IEEE Trans. Inform. Theory. Available at http://www.comm.utoronto.ca/frank/factor.
5. G. D. Forney, Jr. "Codes on graphs: News and views". In Proc. Int. Symp. on Turbo Codes and Related Topics, pp. 916. Brest, France, Sept. 2000.
6. G. D. Forney, Jr. "On iterative decoding and the two-way algorithm". In Proc. Int. Symp. on Turbo Codes and Related Topics. Brest, France, Sept. 1997.
7. H.-A. Loeliger, M. Helfenstein, F. Lustenberger, and F. Tarkoy. "Probability propagation and decoding in analog VLSI". In Proc. ISLT, p. 146. Cambridge, MA, Aug. 1998.
8. F. Lustenberger, M. Helfenstein, H.-A. Loeliger, F. Tarkoy, and G. S. Moschytz. "An analog decoding technique for digital codes". In Proc. ISCAS, vol. II, pp. 428-431. Orlando, FL, June 1999.
9. H.-A. Loeliger, F. Lustenberger, M. Helfenstein, and F. Tarkoy. "Probability propagation and decoding in analog VLSI", Sept. 2000. To appear in IEEE Transactions on Information Theory, available at http://www.isi.ee.ethz.ch/-lustenbe.
10. F. Lustenberger, M. Helfenstein, H.-A. Loeliger, F. Tarkoy, and G. S. Moschytz. "All-analog decoder for a binary (18,9,5) tail-biting trellis code". In Proc. ESSCIRC, pp. 362365. Duisburg, Sep. 1999.
11. F. Lustenberger. On the Design of Analog VLSI Iterative Decoders. Ph.D. thesis, Swiss Federal Institute of Technology, Zurich, November 2000.
12. J. Hagenauer. "Decoding of binary codes with analog networks". In Proc. 1998 Information Theory Workshop, pp. 13-14. San Diego, CA. Feb. 1998.
13. M. Moerz, T. Gabara, R. Yan, and J. Hagenauer. "An analog 0.25MV BiCMOS tailbiting MAP decoder". In Proc. ISSCC, pp. 356-357. San Francisco, CA, Feb. 2000.
14. J. Hagenauer, M. Moerz, and E. Offer. "Analog turbo-networks in VLSI: The next step in turbo decoding and equalization". In Proc. Int. Symp. on Turbo Codes and Related Topics, pp. 209-218. Brest, France, Sept. 2000.
15. M. H. Shakiba, D. A. Johns, and K. W. Martin. "An integrated 200-MHz 3.3-V BiCMOS class-IV partial-response analog Viterbi decoder". IEEE J. Solid-State Circuits, vol. 33, no. 1, pp. 61-75, Jan. 1998.
16. M. H. Shakiba, D. A. Johns, and K. W. Martin. "BiCMOS circuits for analog viterbi decoders". IEEE Trans. CAS-II, vol. 45, no. 12, pp. 1527-1537, Dec. 1998.
17. A. Demosthenous and J. Taylor. "Low-power CMOS and BiCMOS circuits for analog convolutional decoders". IEEE Trans. CAS-II, vol. 46, no. 8, pp. 1077-1080, Aug. 1999.
18. K. He and G. Cauwenberghs. "An area-efficient analog VLSI architecture for state-parallel Viterbi decoding". In Proc. ISCAS, vol. II, pp. 432-135. Orlando, Florida. May 1999.
19. M. J. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers. "Matching properties of MOS transistors". IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433-1439, Oct. 1989.