Post-Si CMOS: III-V n-MOSFETs with high-k gate dielectrics

2007 International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2007

Volumn , Issue , 2007, Pages 231-234

  Sun, Yanning ^a   Koester, S J ^a   Kiewra, E W ^a   De Souza, J P ^a   Ruiz, N ^a   Bucchignano, J J ^a   Callegari, A ^a   Fogel, K E ^a   Sadana, D K ^a   Fompeyrine, J ^b   Webb, D J ^b   Locquet, J P ^b   Sousa, M ^b   Germann, R ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM RESEARCH ZURICH   (Switzerland)

Author keywords

Buried channel; Dielectric; Enhancement mode; High k; III V; Mosfet

Indexed keywords

BURIED-CHANNEL; ENHANCEMENT-MODE; HIGH-K; III-V; MOS-FET;

CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; GATE DIELECTRICS; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON;

MOSFET DEVICES;

EID: 84887430516     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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