Improvements to CBCM (charge-based capacitance measurement) for deep submicron CMOS technology

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2006, Pages 6-11

  Bach, Randy ^a   Davis, Bob ^a   Laubhan, Rich ^a  

^a AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS;

65-NM PROCESS TECHNOLOGY; ACCURACY IMPROVEMENT; ACCURATE MEASUREMENT; CHARGE-BASED CAPACITANCE MEASUREMENTS; CIRCUIT ARCHITECTURES; DEEP-SUBMICRON CMOS TECHNOLOGY; INTERCONNECT CAPACITANCE; NANOMETER TECHNOLOGY;

CAPACITANCE MEASUREMENT;

EID: 84886741177     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2006.74     Document Type: Conference Paper

References (5)

1. J.C. Chen, B.W. McGaughy, D. Sylvester, and C. Hu, "An On-chip Attofarad Interconnect Charge-based Capacitance Measurement (CBCM) technique", IEDM Tech. Dig., 1996, pp. 3.4.1-3.4.4.
2. Nagaraj NS, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras Balsara, Cyrus Cantrell, "Benchmarks for Interconnect Parasitic Resistance and Capacitance," isqed, p. 163, ISQED, 2003.
3. A. Teene, B. Davis, R. Castagnetti, J. Brown, S. Ramesh, "Impact of Interconect Process Variations on Memory Performance and Design", Proceedings of ISQED 2004.
4. R. Lefferts, C. Jakubiec, "An Integrated Test Chip for the Complete Characterization and Monitoring of a 0.25um CMOS Technology that fits into five scribe line structures 150um by 5,000um", ICMTS 03-59.
5. Y.W. Chang, H.W. Chang, C.H. Hsieh, H.C. Lai, T.C. Lu, W. Ting, J. Ku, C.Y. Lu, "A Novel Simple CBCM Method Free From Charge Injection-Induced Errors", IEEE Electron Device Letters, Vol. 25, No. 5, May 2004.