메뉴 건너뛰기




Volumn , Issue , 2005, Pages 648-653

A more effective C/sub EFF/

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITIVE LOADS; CHIP-LEVEL; CLOSED FORM; CPU TIME; EFFECTIVE CAPACITANCE; INTERCONNECT PARASITICS;

EID: 84886686972     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2005.10     Document Type: Conference Paper
Times cited : (5)

References (13)
  • 3
    • 0029776259 scopus 로고    scopus 로고
    • Efficient gate delay modeling for large interconnect loads
    • A. B. Kahng and S. Muddu. Efficient gate delay modeling for large interconnect loads. In Multi-Chip Module Conference, pages 202-207, 1996.
    • (1996) Multi-Chip Module Conference , pp. 202-207
    • Kahng, A.B.1    Muddu, S.2
  • 4
    • 0031704625 scopus 로고    scopus 로고
    • New efficient algorithms for computing effective capacitanc
    • A. B. Kahng and S. Muddu. New efficient algorithms for computing effective capacitanc. In Int'l Symposium on Physical Design, pages 147-151, 1998.
    • (1998) Int'l Symposium on Physical Design , pp. 147-151
    • Kahng, A.B.1    Muddu, S.2
  • 5
    • 0032715195 scopus 로고    scopus 로고
    • Improved effective capacitance computations for use in logic and layout optimization
    • A. B. Kahng and S. Muddu. Improved effective capacitance computations for use in logic and layout optimization. In Int'l Conf. on VLSI Design, pages 578-582, 1999.
    • (1999) Int'l Conf. on VLSI Design , pp. 578-582
    • Kahng, A.B.1    Muddu, S.2
  • 7
    • 0031631926 scopus 로고    scopus 로고
    • A new algorithm for computing the effective capacitance in deep sub-micron circuits
    • R. Macys and S. McCormick. A new algorithm for computing the "effective capacitance" in deep sub-micron circuits. In Custom Integrated Circuits Conference, pages 313-316, 1998.
    • (1998) Custom Integrated Circuits Conference , pp. 313-316
    • MacYs, R.1    McCormick, S.2
  • 8
    • 0026237181 scopus 로고
    • A single-piece c?-continuous MOSFET model including subthreshold conduction
    • Oct
    • C. C. McAndrew, B. K. Bhattacharyya, and O. Wing. A single-piece c?-continuous MOSFET model including subthreshold conduction. IEEE Electron Device Letters, 12(10):565-567, Oct 1991.
    • (1991) IEEE Electron Device Letters , vol.12 , Issue.10 , pp. 565-567
    • McAndrew, C.C.1    Bhattacharyya, B.K.2    Wing, O.3
  • 11
    • 0024906813 scopus 로고
    • Modeling of driving point characteristic of resistive interconnect for accurate delay estimation
    • P. R. O'Brien and L. T. Savarino. Modeling of driving point characteristic of resistive interconnect for accurate delay estimation. In Int'l Conf on Computer Aided Design, pages 512-515, 1989.
    • (1989) Int'l Conf on Computer Aided Design\ , pp. 512-515
    • O'brien, P.R.1    Savarino, L.T.2
  • 12
    • 0028756124 scopus 로고
    • Modeling the 'effective capacitance' for the rc interconnect of cmos gate
    • Dec
    • J. Qian, S. Pullela, and L. T. Pillage. Modeling the 'effective capacitance' for the rc interconnect of cmos gate. IEEE Trans. CAD, 13(12):1526-1535, Dec 1994.
    • (1994) IEEE Trans. CAD , vol.13 , Issue.12 , pp. 1526-1535
    • Qian, J.1    Pullela, S.2    Pillage, L.T.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.