Experimental demonstration of 100nm channel length In0.53Ga 0.47As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2009, Pages

  Mookerjea, S ^a   Mohata, D ^a   Krishnan, R ^a   Singh, J ^a   Vallett, A ^a   Ali, A ^a   Mayer, T ^a   Narayanan, V ^a   Schlom, D ^b   Liu, A ^c   Datta, S ^a  

^a The Center for Nanotechnology Education and Utilization   (United States)

^b School of Chemical and Molecular Engineering   (United States)

^c IQE INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BAND TO BAND TUNNELING; CHANNEL LENGTH; DRAIN BIAS; FORWARD BIAS; GATE BIAS; GATE STACKS; LOW POWER; MEASURED DATA; ON-CURRENTS; ROOM TEMPERATURE; SRAM APPLICATIONS; SRAM CELL; TUNNEL FIELD EFFECT TRANSISTOR; TUNNELING RATES; TWO-DIMENSIONAL NUMERICAL SIMULATION;

COMPUTER SIMULATION; ELECTRON DEVICES; GALLIUM; TUNNELING (EXCAVATION);

FIELD EFFECT TRANSISTORS;

EID: 77952338134     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2009.5424355     Document Type: Conference Paper

References (4)

1. S. Mookerjea et al, Elec. Dev. Lett. Oct (2009)
2. F. Mayer et al IEDM Tech. Dig. 163 (2008)
3. T. Krishnomohan et al, IEDM Tech. Dig. 163 (2008)
4. D. Kim et al, Proc. ISLPED '09 Aug (2009)