Design methodology of a 200 MHz superscalar macroprocessor: SH-4

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 246-249

  Hattori, Toshihiro ^a   Nitta, Yusuke ^a   Seki, Mitsuho ^a   Narita, Susumu ^a   Uchiyama, Kunio ^a   Takahashi, Tsuyoshi ^a   Satomura, Ryuichi ^a  

^a HITACHI LTD   (Japan)

Author keywords

Design methodology; Microprocessor; Timing; Verification

Indexed keywords

BUDGET CONTROL; FORMAL VERIFICATION; MICROPROCESSOR CHIPS; VERIFICATION; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; TIMING CIRCUITS;

DELAY BUDGETING; DESIGN METHODOLOGY; HIGH-SPEED OPERATION; LOGIC EMULATIONS; LOGIC VERIFICATION; RANDOM TEST GENERATION; SUPERSCALAR MICRO-PROCESSORS; TIMING;

DESIGN; MICROPROCESSOR CHIPS;

SUPERSCALAR MICROPROCESSORS;

EID: 0031641256     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Arakawa, F., et al., "SH4 RISC Microprocessor for Multimedia, " Hot CHIPS IX, Aug., 1997.
2. Ishibashi, K., et al., "The Design of 300MIPS Microprocessor with a Full Associative TLB for Handheld PC OS, " Symp. VLSI Circ. Digest ofTechnical Papers, pp. 9-10, June, 1997.
3. Nishii, O. et al., "A 200MHz 1.2W 1.4GFLOPS Microprocessor with Graphic Operation Unit, " Int. Solid-State Circ. Conf., Feb., 1998.
4. Osada, K., et al., "A 2ns Access, 285MHz, Two-Port Cache Macro using Double Global Bit-Line Pairs, " ISSCC Digest of Technical Papers, pp. 402-403, 494, Feb., 1997.