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Volumn 53, Issue 6, 2011, Pages 266-273

Algorithm Engineering Challenges in Multicore and Manycore Systems;Algorithm Engineering Herausforderungen bei Mehrkern- und Manycore-Systemen

Author keywords

Algorithmen; GPU; parallele Programmierung; performance tuning

Indexed keywords

MEMORY ARCHITECTURE;

EID: 84884306681     PISSN: 16112776     EISSN: 21967032     Source Type: Journal    
DOI: 10.1524/itit.2011.0652     Document Type: Article
Times cited : (2)

References (13)
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    • On the architectural requirements for efficient execution of graph algorithms
    • Oslo, Norway Jun
    • D. A. Bader and G. Cong. On the architectural requirements for efficient execution of graph algorithms. In: Proc. of Int?l Conf. on Parallel Processing, pages 547-556, Oslo, Norway, Jun 2005.
    • (2005) Proc. Of Int?l Conf. Of Parallel Processing , pp. 547-556
    • Bader, D.A.1    Cong, G.2
  • 7
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    • 2-d wavelet transform enhancement on general-purpose microprocessors: Memory hierarchy and simd parallelism exploitation
    • Bangalore, India Dec
    • D. Chaver, C. Tenllado, L. Piñuel, M. Prieto, and F. Tirado. 2-D Wavelet Transform Enhancement on General-Purpose Microprocessors: Memory Hierarchy and SIMD Parallelism Exploitation. In: Proc. of Int?l Conf. on High Performance Computing, LNCS 2552, pages 9-21, Bangalore, India, Dec 2002.
    • (2002) Proc. Of Int?l Conf. Of High Performance Computing LNCS 2552 , pp. 9-21
    • Chaver, D.1    Tenllado, C.2    Piñuel, L.3    Prieto, M.4    Tirado, F.5
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    • Optimizing matrix multiplication for a short-vector SIMD architecture-CELL processor
    • J. Kurzak, W. Alvaro, and J. Dongarra. Optimizing matrix multiplication for a short-vector SIMD architecture-CELL processor. In: Parallel Computing, 35(3):138-150, 2009.
    • (2009) Parallel Computing , vol.35 , Issue.3 , pp. 138-150
    • Kurzak, J.1    Alvaro, W.2    Dongarra, J.3
  • 11
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    • Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors
    • T. Y. Morad, U. C. Weiser, A. Kolodnyt, M. Valero, and E. Ayguade. Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors. In: Computer Architecture Letters, 5(1):14-17, 2006.
    • (2006) Computer Architecture Letters , vol.5 , Issue.1 , pp. 14-17
    • Morad, T.Y.1    Weiser, U.C.2    Kolodnyt, A.3    Valero, M.4    Ayguade, E.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.