Optimizing matrix multiplication for a short-vector SIMD architecture - CELL processor

Parallel Computing

Volumn 35, Issue 3, 2009, Pages 138-150

  Kurzak, Jakub ^a   Alvaro, Wesley ^a   Dongarra, Jack ^a,b,c  

^a UNIVERSITY OF TENNESSEE   (United States)

^b OAK RIDGE NATIONAL LABORATORY   (United States)

^c UNIVERSITY OF MANCHESTER   (United Kingdom)

Author keywords

Instruction level parallelism; Loop optimizations; Single Instruction Multiple Data; Synergistic Processing Element; Vectorization

Indexed keywords

CELLS; COMPUTER ARCHITECTURE; COMPUTER GRAPHICS; CYTOLOGY; DATA HANDLING; DIGITAL ARITHMETIC; DIGITAL STORAGE; EIGENVALUES AND EIGENFUNCTIONS; GRAPHICS PROCESSING UNIT; LINEAR SYSTEMS; PROGRAM COMPILERS;

INSTRUCTION LEVEL PARALLELISM; LOOP OPTIMIZATIONS; PROCESSING ELEMENTS; SINGLE INSTRUCTION MULTIPLE DATA; VECTORIZATION;

MATRIX ALGEBRA;

EID: 60649099576     PISSN: 01678191     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.parco.2008.12.010     Document Type: Article

References (49)

1. IBM Corporation, Cell BE Programming Tutorial, November 2007.
2. IBM Corporation, Cell Broadband Engine Programming Handbook, Version 1.1, April 2007.
3. Borkar S. Design challenges of technology scaling. IEEE Micro 19 4 (1999) 23-29
4. Geer D. Industry trends: chip makers turn to multicore processors. Computer 38 5 (2005) 11-13
5. H. Sutter, The free lunch is over: a fundamental turn toward concurrency in software, Dr. Dobb's J. 30(3).
6. K. Asanovic, R. Bodik, B.C. Catanzaro, J.J. Gebis, P. Husbands, K. Keutzer, D.A. Patterson, W.L. Plishker, J. Shalf, S.W. Williams, K.A. Yelick, The Landscape of Parallel Computing Research: A View from Berkeley, Tech. Rep. UCB/EECS-2006-183, Electrical Engineering and Computer Sciences Department, University of California at Berkeley, 2006.
7. Dongarra J.J., Duff I.S., Sorensen D.C., and van der Vorst H.A. Numerical Linear Algebra for High-performance Computers (1998), SIAM
8. Demmel J.W. Applied Numerical Linear Algebra (1997), SIAM
9. Anderson E., Bai Z., Bischof C., Blackford L.S., Demmel J.W., Dongarra J.J., Du Croz J., Greenbaum A., Hammarling S., McKenney A., and Sorensen D. LAPACK Users' Guide (1992), SIAM
10. Blackford L.S., Choi J., Cleary A., D'Azevedo E., Demmel J., Dhillon I., Dongarra J.J., Hammarling S., Henry G., Petitet A., Stanley K., Walker D., and Whaley R.C. ScaLAPACK Users' Guide (1997), SIAM
11. Basic Linear Algebra Technical Forum, Basic Linear Algebra Technical Forum Standard, August 2001.
12. Kågström B., Ling P., and van Loan C. GEMM-based Level 3 BLAS: high-performance model implementations and performance evaluation Benchmark. ACM Trans. Math. Soft. 24 3 (1998) 268-302
13. ATLAS. .
14. GotoBLAS. .
15. E. Chan, E.S. Quintana-Orti, G. Gregorio Quintana-Orti, R. van de Geijn, Supermatrix out-of-order scheduling of matrix operations for SMP and multi-core architectures, in: Nineteenth Annual ACM Symposium on Parallel Algorithms and Architectures SPAA'07, 2007, pp. 116-125.
16. J. Kurzak, J.J. Dongarra, LAPACK Working Note 178: Implementing Linear Algebra Routines on Multi-Core Processors, Tech. Rep. CS-07-581, Electrical Engineering and Computer Science Department, University of Tennessee, 2006.
17. N. Park, B. Hong, V.K. Prasanna, Analysis of memory hierarchy performance of block data layout, in: International Conference on Parallel Processing, 2002.
18. Park N., Hong B., and Prasanna V.K. Tiling, block data layout, and memory hierarchy performance. IEEE Trans. Parallel Distrib. Syst. 14 7 (2003) 640-654
19. J.R. Herrero, J.J. Navarro, Using nonlinear array layouts in dense matrix operations, in: Workshop on State-of-the-Art in Scientific and Parallel Computing PARA'06, 2006.
20. A. Buttari, J. Langou, J. Kurzak, J.J. Dongarra, LAPACK Working Note 190: Parallel Tiled QR Factorization for Multicore Architectures, Tech. Rep. CS-07-598, Electrical Engineering and Computer Science Department, University of Tennessee, 2007.
21. A. Buttari, J. Langou, J. Kurzak, J.J. Dongarra, LAPACK Working Note 191: A Class of Parallel Tiled Linear Algebra Algorithms for Multicore Architectures, Tech. Rep. CS-07-600, Electrical Engineering and Computer Science Department, University of Tennessee, 2007.
22. T. Chen, R. Raghavan, J. Dale, E. Iwata, Cell Broadband Engine Architecture and its First Implementation, A Performance View, November 2005. .
23. Kurzak J., and Dongarra J.J. Implementation of mixed precision in solving systems of linear equations on the CELL processor. Concurrency Comput. Pract. Exper. 19 10 (2007) 1371-1385
24. Kurzak J., Buttari A., and Dongarra J.J. Solving systems of linear equations on the CELL processor using Cholesky factorization. IEEE Trans. Parallel Distrib. Syst. 19 9 (2008) 1175-1186
25. D. Hackenberg, Einsatz und Leistungsanalyse der Cell Broadband Engine, Institut für Technische Informatik, Fakultät Informatik, Technische Universität Dresden, Großer Beleg, February 2007.
26. D. Hackenberg, Fast Matrix Multiplication on CELL Systems, July 2007. .
27. IBM Corporation, ALF for Cell BE Programmer's Guide and API Reference, November 2007.
28. M. Pepe, Multi-Core Framework (MCF), Mercury Computer Systems, Version 0.4.4, October 2006.
29. Mercury Computer Systems, Inc., Scientific Algorithm Library (SAL) Data Sheet, 2006. .
30. IBM Corporation, SIMD Math Library API Reference Manual, November 2007.
31. I. Corporation, Mathematical Acceleration Subsystem-product Overview, March 2007. .
32. TM) Data Sheet, 2006. .
33. European Center for Parallelism of Barcelona, Technical University of Catalonia, Paraver, Parallel Program Visualization and Analysis Tool Reference Manual, Version 3.1, October 2001.
34. IBM Corporation, Software Development Kit 2.1 Programmer's Guide, Version 2.1, March 2007.
35. Strassen V. Gaussian elimination is not optimal. Numer. Math. 13 (1969) 354-356
36. Coppersmith D., and Winograd S. Matrix multiplication via arithmetic progressions. J. Symbol. Comput. 9 3 (1990) 251-280
37. Aberdeen D., and Baxter J. Emmerald: A fast matrix-matrix multiply using Intel's SSE instructions. Concurrency Comput. Pract. Exper. 13 2 (2001) 103-119
38. S. Williams, J. Shalf, L. Oliker, S. Kamil, P. Husbands, K. Yelick, The potential of the cell processor for scientific computing, in: ACM International Conference on Computing Frontiers, 2006.
39. Williams S., Shalf J., Oliker L., Kamil S., Husbands P., and Yelick K. Scientific computing kernels on the cell processor. Int. J. Parallel Prog. 35 3 (2007) 263-298
40. IBM Corporation, Basic Linear Algebra Subprograms Programmer's Guide and API Reference, November 2007.
41. B. Flachs, S. Asano, S.H. Dhong, P. Hofstee, G. Gervais, R. Kim, T. Le, P. Liu, J. Leenstra, J. Liberty, B. Michael, H. Oh, S.M. Mueller, O. Takahashi, A. Hatakeyama, Y. Watanabe, N. Yanoz, A streaming processing unit for a CELL processor, in: IEEE International Solid-State Circuits Conference, 2005, pp. 134-135.
42. Flachs B., Asano S., Dhong S.H., Hofstee H.P., Gervais G., Roy K., Le T., Peichun L., Leenstra J., Liberty J., Michael B., Hwa-Joon O., Mueller S.M., Takahashi O., Hatakeyama A., Watanabe Y., Yano N., Brokenshire D.A., Peyravian M., Vandung T., and Iwata E. The microarchitecture of the synergistic processor for a cell processor. IEEE J. Solid-State Circ. 41 1 (2006) 63-70
43. Gschwind M., Hofstee H.P., Flachs B., Hopkins M., Watanabe Y., and Yamazaki T. Synergistic processing in cell's multicore architecture. IEEE Micro 26 2 (2006) 10-24
44. Hennessy J.L., and Patterson D.A. Computer Architecture: A Quantitative Approach. fourth ed. (2006)
45. Muchnick S. Advanced Compiler Design and Implementation (1997), Morgan Kaufmann
46. IBM Corporation, Preventing synergistic processor element indefinite stalls resulting from instruction depletion in the Cell Broadband Engine Processor for CMOS SOI 90 nm, Applications Note, Version 1.0, November 2007.
47. Dongarra J.J., Luszczek P., and Petitet A. The LINPACK Benchmark: past, present and future. Concurrency Comput. Pract. Exper. 15 9 (2003) 803-820
48. TOP500 Supercomputing Sites. .
49. Shin J., Chame J., and Hall M.W. Exploiting superword-level locality in multimedia extension architectures. J. Instr. Level Parallel. 5 (2003) 1-28