Active guardband management in power7+ to save energy and maintain reliability

IEEE Micro

Volumn 33, Issue 4, 2013, Pages 35-45

  Lefurgy, Charles R ^a   Drake, Alan J ^a   Floyd, Michael S ^a   Allen Ware, Malcolm S ^a   Brock, Bishop ^a   Tierno, José A ^b   Carter, John B ^a   Berry, Robert W ^a  

^a IBM   (United States)

^b Apple ^*  (United States)

Author keywords

Critical path; Design; Digital phase lock loop; Energy efficient; Experimentation; Measurement; Performance; Performance and reliability; Power7+; Reliability; Timing margin; Voltage speculation

Indexed keywords

CRITICAL PATHS; DIGITAL PHASE-LOCK LOOPS; ENERGY EFFICIENT; EXPERIMENTATION; PERFORMANCE; PERFORMANCE AND RELIABILITIES; POWER7; TIMING MARGIN;

CLOCKS; DESIGN; ENERGY EFFICIENCY; FIRMWARE; MEASUREMENTS; MICROPROCESSOR CHIPS; RELIABILITY;

TIMING CIRCUITS;

EID: 84883324967     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2013.52     Document Type: Article

References (4)

1. C. Lefurgy et al., Active Management of Timing Guardband to Save Energy in POWER7, Proc. 44th Ann. Intl Symp. Microarchitecture, ACM, 2011, pp. 1-11.
2. A. Drake et al., A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor, Proc. Intl Solid-State Circuits Conf. (ISSCC 07), IEEE, 2007, pp. 398- 399.
3. M. Floyd et al., Introducing the Adaptive Energy Management Features of the Power7 Chip, IEEE Micro, Mar./Apr. 2011, pp. 60-75.
4. J.A. Tierno, A.V. Rylyakov, and D.J. Friedman, A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI, IEEE J. Solid-State Circuits, Jan. 2008, pp. 42-51.