Nano-silica composite laminate

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2013, Pages 929-936

  Hayashi, Katsura ^a   Nagasawa, Tadashi ^a   Matsumoto, Keisaku ^a   Kawai, Shinya ^a  

^a KYOCERA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPOSITE LAMINATE; DIELECTRIC TEST; DIELECTRICITY; NANO-SILICA; PACKAGING PROCESS; PACKAGING TECHNOLOGIES; SILICON CHIP; TEMPERATURE RISE;

CHIP SCALE PACKAGES; DIELECTRIC MATERIALS; LAMINATED COMPOSITES; PACKAGING; RESINS; SUBSTRATES; TECHNOLOGY;

NANOCOMPOSITE FILMS;

EID: 84883323406     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2013.6575686     Document Type: Conference Paper

References (4)

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2. Mohammad M Hossain, Srinivasa R Aravamudhan, Marilyn Nowakowski, Xiaoqing Ma, Satyajit S Walwadkar, Vijay Kulkarni, Sriram Muthukumar, "Board Level Solder Joint Assembly and Reliability for Ultra Thin BGA Packages," in Proc. IEEE Electronic Components and Technol. Conf. (ECTC), San Diego, CA, May 29-Jun 1, 2012, pp. 43-48
3. Katsuyuki Sakuma, Kurt Smith, Krishna Tunga, Eric Perfecto, Thomas Wassick,Frank Pompeo, and Jae-Woong Nah, "Differential Heating/Cooling Chip Joining Method to Prevent Chip Package Interaction Issue in Large Die with Ultra Low-k Technology," in Proc. IEEE Electronic Components and Technol. Conf. (ECTC), San Diego, CA, May 29-Jun 1, 2012, pp. 430-435
4. Shin-Etsu Quartz Products Co., Ltd, Product Information Catalogs "Technology Guidance of Quartz Glass-1 (Japanese)," http://www.sqp.co.jp/e/index.htm.