Neural network based on a three-terminal ferroelectric memristor to enable on-chip pattern recognition

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2013, Pages

  Kaneko, Yukihiro ^a   Nishitani, Yu ^a   Ueda, Michihito ^a   Tsujimura, Ayumu ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

ferroelectric; memristor; neural network; non volatile memory; pattern recognition

Indexed keywords

CMOS CIRCUITS; MATRIX PATTERNS; MEMRISTOR; NON-VOLATILE; NON-VOLATILE MEMORY; ON CHIPS; SYNAPTIC WEIGHT;

CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; FERROELECTRIC MATERIALS; FERROELECTRICITY; MEMRISTORS; PASSIVE FILTERS; PATTERN RECOGNITION; VLSI CIRCUITS;

NEURAL NETWORKS;

EID: 84883312937     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. M. Suri et al., J. Appl. Phys., vol. 112, pp. 054904, 2012.
2. Y. Wu et al., 4th IEEE Int. Memory Workshop, 2012.
3. Y. Kaneko et al., Appl. Phys. Lett., vol. 99, pp. 182902, 2011.
4. G.Q. Bi et al., J. Neurosci., vol. 18, pp. 10464, 1998.