Main-memory hash joins on multi-core CPUs: Tuning to the underlying hardware

Proceedings - International Conference on Data Engineering

Volumn , Issue , 2013, Pages 362-373

  Balkesen, Cagri ^a   Teubner, Jens ^a   Alonso, Gustavo ^a   Özsu, M Tamer ^b  

^a ETH ZURICH   (Switzerland)

^b UNIVERSITY OF WATERLOO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL CHANGES; ARCHITECTURAL PARAMETERS; DATA OPERATORS; EXPERIMENTAL ANALYSIS; JOIN ALGORITHM; MEMORY BANDWIDTHS; MULTI-CORE CPUS; PARAMETERS SETTING;

ALGORITHMS; PARAMETER ESTIMATION; PROGRAM PROCESSORS;

HARDWARE;

EID: 84881338673     PISSN: 10844627     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICDE.2013.6544839     Document Type: Conference Paper

References (21)

1. C. Kim, E. Sedlar, J. Chhugani, T. Kaldewey, A. D. Nguyen, A. D. Blas, V. W. Lee, N. Satish, and P. Dubey, "Sort vs. hash revisited: Fast join implementation on modern multi-core CPUs," PVLDB, vol. 2, no. 2, pp. 1378-1389, 2009.
2. S. Blanas, Y. Li, and J. M. Patel, "Design and evaluation of main memory hash join algorithms for multi-core CPUs," in SIGMOD Conference, 2011, pp. 37-48.
3. M.-C. Albutiu, A. Kemper, and T. Neumann, "Massively parallel sort-merge joins in main memory multi-core database systems," PVLDB, vol. 5, no. 10, pp. 1064-1075, 2012.
4. S. Manegold, P. A. Boncz, and M. L. Kersten, "Optimizing main-memory join on modern hardware," IEEE Trans. Knowl. Data Eng., vol. 14, no. 4, pp. 709-730, 2002.
5. M. T. Özsu and P. Valduriez, Principles of Distributed Database Systems, 3rd edition. Springer, 2012.
6. M. Kitsuregawa, H. Tanaka, and T. Moto-Oka, "Application of hash to data base machine and its architecture," New Generation Comput., vol. 1, no. 1, pp. 63-74, 1983.
7. A. Shatdal, C. Kant, and J. F. Naughton, "Cache conscious algorithms for relational query processing," in VLDB, 1994, pp. 510-521.
8. P. A. Boncz, S. Manegold, and M. L. Kersten, "Database architecture optimized for the new bottleneck: Memory access," in VLDB, 1999, pp. 54-65.
9. A. Ailamaki, D. J. DeWitt, M. D. Hill, and D. A. Wood, "DBMSs on a modern processor: Where does time go?" in VLDB, 1999, pp. 266-277.
10. S. Manegold, P. Boncz, N. Nes, and M. Kersten, "Cache-conscious radix-decluster projections," in VLDB, Toronto, ON, Canada, Sep. 2004, pp. 684-695.
11. "Intel performance counter monitor," http://software.intel.com/ en-us/articles/intel-performance-counter-monitor/, online, accessed April 2012.
12. S. Blanas and J. M. Patel, "Source code of main-memory hash join algorithms for multi-core CPUs," http://pages.cs.wisc.edu/∼sblanas/ files/multijoin.tar.bz2, online, accessed April 2012.
13. P. Conway, N. Kalyanasundharam, G. Donley, K. Lepak, and B. Hughes, "Cache hierarchy and memory subsystem of the AMD Opteron processor," IEEE Micro, vol. 30, no. 2, pp. 16-29, Mar. 2010.
14. A. Fog, "Instruction tables: Lists of instruction latencies, throughputs and micro-operation breakdowns for Intel, AMD and VIA CPUs," http://www.agner.org/optimize/instruction tables.pdf, online, accessed July 2012.
15. Sun, "UltraSPARC T2TM supplement to the UltraSPARC architecture 2007," http://sosc-dr.sun.com/processors/UltraSPARC-T2/docs/UST2-UASuppl- HP-ext.pdf, online, accessed July 2012.
16. Intel, "Intel 64 and IA-32 architectures optimization reference manual," http://www.intel.com/content/dam/doc/manual/64-ia-32- architectures-optimization-manual.pdf, online, accessed July 2012.
17. C. Balkesen, J. Teubner, G. Alonso, and M. T. Özsu, "Main-memory hash joins on multi-core CPUs: Tuning to the underlying hardware," ETH Zurich, Systems Group, Tech. Rep., Nov. 2012.
18. G. Graefe, "Robust query processing," in ICDE, 2011, p. 1361.
19. Y. Ye, K. A. Ross, and N. Vesdapunt, "Scalable aggregation on multicore processors," in DaMoN, 2011, pp. 1-9.
20. J. Teubner and R. Müller, "How soccer players would do stream joins," in SIGMOD Conference, 2011, pp. 625-636.
21. T. Kaldewey, G. M. Lohman, R. Müller, and P. B. Volk, "GPU join processing revisited," in DaMoN, 2012, pp. 55-62.