Sort vs. hash revisited: Fast join implementation on modern multicore CPUs

Proceedings of the VLDB Endowment

Volumn 2, Issue 2, 2009, Pages 1378-1389

  Kim, Changkyu ^a   Sedlar, Eric ^b   Chhugani, Jatin ^a   Kaldewey, Tim ^b   Nguyen, Anthony D ^a   Blas, Andrea Di ^b   Lee, Victor W ^a   Satish, Nadathur ^a   Dubey, Pradeep ^a  

^a INTEL CORPORATION   (United States)

^b ORACLE CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HASH FUNCTIONS; PROGRAM PROCESSORS;

CHIP MULTIPROCESSOR; INPUT DATAS; INTEL CORE I7; JOIN ALGORITHM; MEMORY BANDWIDTHS; MULTI-CORE CPUS; PARALLEL VERSION; PROCESSOR ARCHITECTURES;

COMPUTER ARCHITECTURE;

EID: 77954705147     PISSN: None     EISSN: 21508097     Source Type: Conference Proceeding    
DOI: 10.14778/1687553.1687564     Document Type: Article

References (39)

1. N. Askitis and J. Zobel. Cache-conscious collision resolution in string hash tables. In in Proc. String Processing and Information Retrieval Symposium (SPIRE, pages 92-104, 2005.
2. K. E. Batcher. Sorting networks and their applications. In Spring Joint Computer Conference, pages 307-314, 1968.
3. M. W. Blasgen and K. P. Eswaran. Storage and access in relational data bases. IBM Systems Journal, 16(4):362-377, 1977.
4. G. E. Blelloch. Synthesis of Parallel Algorithms, chapter Prefix sums and their applications, pages 35-60. Morgan Kaufmann, 1993.
5. P. A. Boncz, S. Manegold, and M. L. Kersten. Database architecture optimized for the new bottleneck: Memory access. In VLDB, pages 54-65, 1999.
6. S. Chen, A. Ailamaki, P. B. Gibbons, and T. C. Mowry. Improving hash join performance through prefetching. In ICDE, pages 116-127, 2004.
7. J. Chhugani, A. D. Nguyen, V. W. Lee, W. Macy, M. Hagog, Y.-K. Chen, A. Baransi, S. Kumar, and P. Dubey. Efficient implementation of sorting on multi-core SIMD CPU architecture. VLDB, pages 1313-1324, 2008.
8. J. Cieslewicz and K. A. Ross. Adaptive aggregation on chip multiprocessors. In VLDB, pages 339-350, 2007.
9. J. Cieslewicz and K. A. Ross. Data partitioning on chip multiprocessors. In DaMoN, pages 25-34, 2008.
10. D. J. DeWitt and R. H. Gerber. Multiprocessor hash-based join algorithms. In VLDB, pages 151-164, 1985.
11. J. Doweck. Inside Intel core microarchitecture and smart memory access. White Paper, Intel Corporation Jul 2006.
12. B. Gedik, P. S. Yu, and R. Bordawekar. Executing stream joins on the cell processor. In VLDB, pages 363-374, 2007.
13. N. Govindaraju, J. Gray, R. Kumar, and D. Manocha. GPUTeraSort: High Performance Graphics Co-processor Sorting for Large Database Management. In Proceedings of the ACM SIGMOD Conference, pages 325-336, 2006.
14. G. Graefe, A. Linville, and L. D. Shapiro. Sort versus hash revisited. IEEE Trans. Knowl. Data Eng., 6(6):934-944, 1994.
15. J. Gray, P. Sundaresan, S. Englert, K. Baclawski, and P. J. Weinberger. Quickly generating billion-record synthetic databases. In SIGMOD Conference, pages 243-252, 1994.
16. A. Greß and G. Zachmann. GPU-ABiSort: Optimal Parallel Sorting on Stream Architectures. In Proceedings of the 20th IEEE International Parallel and Distributed Processing Symposium, page 45, Apr. 2006.
17. N. Hardavellas, I. Pandis, R. Johnson, N. Mancheril, A. Ailamaki, and B. Falsafi. Database servers on chip multiprocessors: Limitations and opportunities. In CIDR, pages 79-87, 2007.
18. B. He, K. Yang, R. Fang, M. Lu, N. K. Govindaraju, Q. Luo, and P. V. Sander. Relational joins on graphics processors. In SIGMOD Conference, pages 511-524, 2008.
19. W. D. Hillis and G. L. Steele, Jr. Data parallel algorithms. Commun. ACM, 29(12):1170-1183, 1986.
20. K. A. Hua and C. Lee. Handling data skew in multiprocessor database computers using partition tuning. In VLDB, pages 525-535, 1991.
21. Intel Advanced Vector Extensions Programming Reference. 2008, http://softwarecommunity.intel.com/isn/downloads/intelavx/Intel-AVXProgramming-Reference-31943302.pdf.
22. Intel SSE4 programming reference. 2007, http://www.intel.com/design/processor/manuals/253667.pdf.
23. M. Kitsuregawa, H. Tanaka, and T. Moto-Oka. Application of hash to data base machine and its architecture. New Generation Comput., 1(1), 1983.
24. S. Kumar, D. Kim, M. Smelyanskiy, Y.-K. Chen, J. Chhugani, C. Hughes, C. Kim, V. Lee, and A. Nguyen. Atomic vector operations on chip multiprocessors. In 35th International Symposium on Computer Architecture, pages 441-452, June 2008.
25. T. J. Lehman and M. J. Carey. A study of index structures for main memory database management systems. In VLDB '86: Proceedings of the 12th International Conference on Very Large Data Bases, pages 294-303, 1986.
26. H. Lu, K.-L. Tan, and M.-C. Shan. Hash-based join algorithms for multiprocessor computers. In D. McLeod, R. Sacks-Davis, and H.-J. Schek, editors, VLDB, pages 198-209, 1990.
27. S. Manegold, P. A. Boncz, and M. L. Kersten. What happens during a join? dissecting cpu and memory optimization effects. In VLDB, pages 339-350, 2000.
28. S. Manegold, P. A. Boncz, and M. L. Kersten. Optimizing main-memory join on modern hardware. IEEE Trans. Knowl. Data Eng., 14(4):709-730, 2002.
29. E. Mohr, D. A. Kranz, and R. H. Halstead. Lazy task creation: a technique for increasing the granularity of parallel programs. IEEE Transactions on Parallel and Distributed Systems, 2:185-197, 1991.
30. R. Motwani and P. Raghvan. Randomized Algorithms. Cambridge University Press, 1995.
31. C. Nyberg, T. Barclay, Z. Cvetanovic, J. Gray, and D. Lomet. Alphasort: a risc machine sort. SIGMOD Rec., 23(2):233-242, 1994.
32. T. J. Purcell, C. Donner, M. Cammarano, H. W. Jensen, and P. Hanrahan. Photon Mapping on Programmable Graphics Hardware. In Graphics Hardware 2003, pages 41-50, July 2003.
33. M. Reilly. When multicore isn't enough: Trends and the future for multi-multicore systems. In HPEC, 2008.
34. L. Seiler, D. Carmean, E. Sprangle, T. Forsyth, M. Abrash, P. Dubey, S. Junkins, A. Lake, J. Sugerman, R. Cavin, R. Espasa, E. Grochowski, T. Juan, and P. Hanrahan. Larrabee: A Many-Core x86 Architecture for Visual Computing. Proceedings of SIGGRAPH, 27(3), 2008.
35. A. Shatdal, C. Kant, and J. F. Naughton. Cache conscious algorithms for relational query processing. In VLDB, pages 510-521, 1994.
36. J. L. Wolf, D. M. Dias, and P. S. Yu. A parallel sort merge join algorithm for managing data skew. IEEE Trans. Parallel Distrib. Syst., 4(1):70-86, 1993.
37. J. L. Wolf, P. S. Yu, J. Turek, and D. M. Dias. A parallel hash join algorithm for managing data skew. IEEE Trans. Parallel Distrib. Syst., 4(12):1355-1371, 1993.
38. H. Zeller and J. Gray. An adaptive hash join algorithm for multiuser environments. In VLDB, pages 186-197, 1990.
39. J. Zhou and K. A. Ross. Implementing database operations using simd instructions. In SIGMOD Conference, pages 145-156, 2002.