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Volumn , Issue , 2013, Pages

Underpowering NAND flash: Profits and perils

Author keywords

[No Author keywords available]

Indexed keywords

NAND FLASH; SERVER SYSTEM; SUPPLY-VOLTAGE FLUCTUATION; VOLTAGE DROOP;

EID: 84879870283     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2463209.2488935     Document Type: Conference Paper
Times cited : (10)

References (14)
  • 1
    • 84871152682 scopus 로고    scopus 로고
    • Umass trace repository. http://traces.cs.umass.edu/index.php/Storage/ Storage.
    • Umass Trace Repository
  • 8
    • 33750071521 scopus 로고    scopus 로고
    • Low-energy heterogeneous non-volatile memory systems for mobile systems
    • H. G. Lee and N. Chang. Low-energy heterogeneous non-volatile memory systems for mobile systems. Journal of Low Power Electronics, 1:52-62, 2005.
    • (2005) Journal of Low Power Electronics , vol.1 , pp. 52-62
    • Lee, H.G.1    Chang, N.2
  • 10
    • 34247364655 scopus 로고    scopus 로고
    • Ultra-low power data storage for sensor networks
    • IPSN 2006. The Fifth International Conference on, 0-0
    • G. Mathur, P. Desnoyers, D. Ganesan, and P. Shenoy. Ultra-low power data storage for sensor networks. In Information Processing in Sensor Networks, 2006. IPSN 2006. The Fifth International Conference on, pages 374 -381, 0-0 2006.
    • (2006) Information Processing in Sensor Networks, 2006 , pp. 374-381
    • Mathur, G.1    Desnoyers, P.2    Ganesan, D.3    Shenoy, P.4
  • 12
    • 56549115024 scopus 로고    scopus 로고
    • Improving energy efficiency for flash memory based embedded applications
    • January
    • H. Song, S. Choi, H. Cha, and R. Ha. Improving energy efficiency for flash memory based embedded applications. Journal of System Architecture, 55:15-24, January 2009.
    • (2009) Journal of System Architecture , vol.55 , pp. 15-24
    • Song, H.1    Choi, S.2    Cha, H.3    Ha, R.4
  • 13
    • 0032140032 scopus 로고    scopus 로고
    • A multipage cell architecture for high-speed programming multilevel NAND flash memories
    • Aug
    • K. Takeuchi, T. Tanaka, and T. Tanzawa. A multipage cell architecture for high-speed programming multilevel NAND flash memories. IEEE Journal of Solid-State Circuits, 33(8):1228 -1238, Aug. 1998.
    • (1998) IEEE Journal of Solid-State Circuits , vol.33 , Issue.8 , pp. 1228-1238
    • Takeuchi, K.1    Tanaka, T.2    Tanzawa, T.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.