Runtime dependency analysis for loop pipelining in high-level synthesis

Proceedings - Design Automation Conference

Volumn , Issue , 2013, Pages

  Alle, Mythri ^a   Morvan, Antoine ^b   Derrien, Steven ^a  

^a UNIVERSITÉ DE RENNES 1   (France)

^b INRIA   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DEPENDENCY ANALYSIS; HIGH LEVEL SYNTHESIS; LOOP PIPELINING; MEMORY DISAMBIGUATION; PERFORMANCE IMPROVEMENTS; SOURCE TRANSFORMATION; STATIC SCHEDULING; SUPERSCALAR PROCESSOR;

TOOLS;

COMPUTER AIDED DESIGN;

EID: 84879866783     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2463209.2488796     Document Type: Conference Paper

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