A variant of parallel plane sweep algorithm for multicore systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 32, Issue 6, 2013, Pages 966-970

  Khlopotine, Andrei B ^a   Jandhyala, Vikram ^a   Kirkpatrick, Desmond ^b  

^a UNIVERSITY OF WASHINGTON   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Computational geometry; multicore; physical design; plane sweep; rectangle intersection

Indexed keywords

DESIGN AND IMPLEMENTATIONS; DESIGN RULE CHECKING; MULTI CORE; MULTI-CORE MACHINES; PHYSICAL DESIGN; PLANE SWEEP; RECTANGLE INTERSECTIONS; RESISTANCE CAPACITANCE;

DESIGN; INTEGRATED CIRCUIT LAYOUT;

COMPUTATIONAL GEOMETRY;

EID: 84877918686     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2013.2245940     Document Type: Article

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