Geometric algorithms for private-cache chip multiprocessors (extended abstract)

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 6347 LNCS, Issue PART 2, 2010, Pages 75-86

  Ajwani, Deepak ^a   Sitchinava, Nodari ^a   Zeh, Norbert ^b  

^a AARHUS UNIVERSITY   (Denmark)

^b DALHOUSIE UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE CHIPS; CONVEX HULL; EFFICIENT ALGORITHM; EXTENDED ABSTRACTS; GEOMETRIC ALGORITHM; GEOMETRIC PROBLEMS; LINE SEGMENT INTERSECTION; LOAD BALANCING STRATEGY; LOWER ENVELOPES; MERGE-SORT ALGORITHM; OPTIMAL ALGORITHM; PARALLEL DISTRIBUTION; PRAM ALGORITHMS; SECOND GROUP;

MULTIPROCESSING SYSTEMS; OPTIMIZATION;

ALGORITHMS;

EID: 78349263882     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-15781-3_7     Document Type: Conference Paper

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