Shared cache aware task mapping for WCRT minimization

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2013, Pages 735-740

  Ding, Huping ^a   Liang, Yun ^b   Mitra, Tulika ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b PEKING UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

EXPERIMENTAL EVALUATION; INTEGER-LINEAR PROGRAMMING; MULTI-CORE SYSTEMS; REAL-TIME EMBEDDED SYSTEMS; SYNTHETIC APPLICATION; TRADITIONAL APPROACHES; WORST CASE RESPONSE TIME; WORST-CASE EXECUTION TIME;

COMPUTER AIDED DESIGN; EMBEDDED SYSTEMS; MAPPING; PARALLEL ARCHITECTURES;

MULTIPROCESSING SYSTEMS;

EID: 84877733553     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2013.6509688     Document Type: Conference Paper

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