CACH-FTL: A cache-aware configurable hybrid flash translation layer

Proceedings of the 2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2013

Volumn , Issue , 2013, Pages 94-101

  Boukhobza, Jalil ^a   Olivier, Pierre ^a   Rubini, Stéphane ^a  

^a not available

Author keywords

Cache; Flash Translation Layer (FTL); NAND Flash Memory; Solid State Drive (SSD); Storage

Indexed keywords

CACHE MEMORY; FLASH-BASED SSDS; MEMORY ARCHITECTURE; NAND CIRCUITS;

CACHE; CACHE SYSTEMS; ERASE OPERATION; FLASH TRANSLATION LAYER; MEMORY USAGE; NAND FLASH MEMORY; PAGE MAPPINGS; PERFORMANCE; SOLID STATE DRIVE;

MAPPING;

EID: 84877647349     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PDP.2013.71     Document Type: Conference Paper

References (21)

1. Market Research, "Advanced Solid State Non-Volatile Memory Market to Grow 69% Annually through 2015", from http://www.marketresearch.com/ corporate/aboutus/press.asp?view=3&article=2223, MarketResearch press release, 2012
2. J. Carter, K. Rajamani, "Designing Energy Efficient Servers and Data Centers", Computer, 43(7), 2010, 76-78.
3. T. Chung, D. Park, S. Park, D. Lee, S. Lee, H. Song, "A Survey of Flash Translation Layer", Journal of Systems Architecture, 55, 2009, pp 332-343.
4. A. Gupta, Y. Kim, B. Urgaonkar, "DFTL: A Flash Translation Layer Employing Demand-based Selective Caching of Page-level Address Mappings", In Proceedings of the 14th ACM International conference on Architectural support for programming languages and operating systems (ASPLOS '09), New York, 2009.
5. A. Ban, "Flash File System Optimized for Page-mode Flash Technologies", United States Patent, No 5,937,425, 1999.
6. J. Kim, J. M. Kim, S. H. Noh, S. L. Min, Y. Cho, "A Space-Efficient Flash Translation Layer for Compact Flash Systems", IEEE Transactions on Consumer Electronics, 48(2), 2002, pp 366-375. (Pubitemid 34798899)
7. C. Wu, T. Kuo, "An Adaptive Two -level Management for the Flash Translation Layer in Embedded Systems", In Proceedings of the 2006 IEEE/ACM international conference on Computer-Aided Design (ICCAD), 2006.
8. S. W. Lee, D. J. Park, T. S. Chung, D. H. Lee, S. Park, H. J. Song, "A Log Buffer Based Flash Translation Layer Using Fully Associative Sector Translation ", ACM Transactions on Embedded Computing Systems, 6(3), 2007, pp 1-27.
9. Y. Wang, D. Liu, M. Wang, Z. Qin, Y. Guan, "RNFTL: a Reuse-aware NAND Flash Translation Layer for Flash Memory", In Proceedings of the ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems (LCTES), 2010.
10. S. Lee, D. Shin, Y. Kim, J. Kim, "LAST: Locality Aware Sector Translation for NAND Flash Memory Based Storage Systems", ACM SIGOPS Operating Systems Review, 42(6), 2008, pp 36-42.
11. Q. Wei, B. Gong, S. Pathak, B. Veeravalli, L. Zeng, K. Okada, "WAFTL: A Workload Adaptive Flash Translation Layer with Data Partition", In Proceedings of 2011 IEEE 27th Symposium on Mass Storage Systems and Technologies (MSST), 2011.
12. S. Kang, S. Park, H. Jung, H. Shim, J. Cha, "Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices", IEEE Transactions on Computers, 58(6), 2009, pp 744-758.
13. H. Jo, J. Kang, S. Park, J. Kim, J. Lee, "FAB: a Flash-aware Buffer Management Policy for Portable Media Players", IEEE Transactions on Consumer Electronics, 52(2),2006, pp 485-493. (Pubitemid 44203122)
14. th USENIX Conference on File and Storage Technologies (FAST), 2008.
15. th Symposium on Mass Storage Systems and Technologies (MSST), 2010.
16. J. Boukhobza, P. Olivier, S. Rubini, "A Cache Management Strategy to Replace Wear Leveling Techniques for Embedded Flash Memory", International Symposium on Performance Evaluation of Computer & Telecommunication Systems (SPECTS), June 2011.
17. G. R. Ganger, B. Worthington, Y. N. Patt, "The Disksim Simulation Environment Version 3.0 Reference Manual ", Tech. Report CMU-CS-03-102, Pittsburgh, 2003.
18. N. Agrawal, V. Prabhakaran, T. Wobber, J. D. Davis, M. Manasse, R. Panigrahy, "Design Tradeoffs for SSD Performance", In Proceedings of the USENIX Annual Technical Conference, 2008.
19. Storage Performance Council, http://www.storageperformance.org
20. OLTP Traces, UMass Trace Repository, http://traces.cs.umass.edu/index. php/Storage/Storage
21. Cello99 Traces, HP Labs. http://tesla.hpl.hp.com/opensource/cello99.