Evolutionary synthesis of fractional capacitor using simulated annealing method

Radioengineering

Volumn 21, Issue 4, 2012, Pages 1252-1259

  Slezák, Josef ^a   Götthans, Tomáš ^a   Dřínovský, Jiří ^a  

^a BRNO UNIVERSITY OF TECHNOLOGY   (Czech Republic)

Author keywords

Automated circuit synthesis; Evolutionary electronics; Simulated annealing

Indexed keywords

EID: 84876978234     PISSN: 12102512     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (22)

1. KOZA, J. Genetic Programming: On the Programming of Computers by Means of Natural Selection. Cambridge (MA, USA): MIT Press, 1992.
2. GRIMBLEBY, J. B. Automatic analogue circuit synthesis using genetic algorithms. IEE Proceedings, 2000, vol. 147, no. 6, p. 319-323.
3. ZEBULUM, R. S., PACHECO, M. A., VELLASCO, M. M. Evolutionary Electronics: Automatic Design of Electronic Circuits and Systems by Genetic Algorithms. Boca Raton (FL, USA): CRC Press, 2001.
4. DAS, A., VEMURI, R. An automated passive analog circuit synthesis framework using genetic algorithms. In IEEE Computer Society Annual Symposium on VLSI. Porto Alegre (Brazil), 2007, p. 145-152.
5. KIRKPATRICK, S., GELLAT, C., VECCHI, M. Optimization by simulated annealing. Science, 1983, vol. 220, no. 4598, p. 671-680.
6. 1/n by a regular Newton process. IEEE Transactions on Circuit Theory, 1964, vol. 11, no. 2, p. 210-213.
7. HARTLEY, T., LORENZO, C., QAMMER, H. K. Chaos in a fractional order Chua's system. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 1995, vol. 42, no. 8, p. 485-490.
8. -1/2. IEEE Transactions on Circuit Theory, 1964, vol. 11, no. 1, p. 160-161.
9. ORTIGUEIRA, M. D. An introduction to the fractional continuoustime linear systems. IEEE Circuits and Systems Magazine, 2008, vol. 8, no. 3., p. 19-26.
10. MATTIUSSI, C., FLOREANO, D. Analog genetic encoding for the evolution of circuits and networks. IEEE Transactions on Evolutionary Computation, 2007, vol. 11, no. 5, p. 596-607.
11. MESQUITE, A., SALAZAR, F. A., CANAZIO, P. P. Chromosome representation through adjacency matrix in evolutionary circuits synthesis. In Proceedings of NASA/DoD Conference on Evolvable Hardware. Washington D.C. (USA), 2002, p. 102-109.
12. LOHN, J. D., COLOMBANO, S. P. A circuit representation technique for automated circuit design. IEEE Transactions on Evolutionary Computation, 1999, vol. 3, no. 3, p. 205-219.
13. TORRES, A., PONCE, E. E., TORRES, M. D., DIAZ, E., PADILLA, F. Comparison of two evolvable systems in the automated analog circuit synthesis. In Eighth Mexican International Conference on Artificial Intelligence. Guanajuato (Mexico), 2009, p. 3-8.
14. RODRIGUEZ, J. L., GARCIA-TUNON, I., TABOADA, J. M., BASTEIRO, F. O. Broadband HF antenna matching network design using a real-coded genetic algorithm. IEEE Transactions on Antennas and Propagation, 2007, vol. 55, no. 3, p. 611-618.
15. ZINCHENKO, L., MUHLENBEIN, H., KUREICHIK, V., MAHNING, T. Application of the univariate marginal distribution algorithm to analog circuit design. In Proceedings of NASA/DoD Conference on Evolvable Hardware. Washington D.C. (USA), 2002, p. 93-101.
16. OCHOTTA, E. S., RUTEMBAR, R. A., CARLEY, L. R. Synthesis of high-performance analog circuits in ASTRX/OBLX. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1996, vol. 15, no. 3, p. 273-294.
17. INGBER, L. Very fast simulated re-annealing. Mathematical and Computer Modelling, 1989, vol. 12, no. 8, p. 967-973.
18. PETŘŽELA, J., GÖTTHANS, T., HRUBOš, Z. Modeling deterministic chaos using electronic circuits. Radioengineering, 2011, vol. 20, no. 2, p. 438-444.
19. PETŘŽELA, J., DŘíNOVSKý, J. High frequency chaos converters. In IEEE Region 8 International Conference on Computational Technologies in Electrical and Electronics Engineering (SIBIRCON). Irkutsk Listvyanka (Russia), 2010, p. 750-754.
20. KOLKA, Z. SNAP - Program for Symbolic Analysis. Radioengineering, 1999, vol. 8, no. 1, p. 23-24.
21. VALSA, J., DVORAK, P., FRIEDL, M. Network Model of the CPE. Radioengineering, 2011, vol. 20, no. 3, p. 619-626.
22. DŘíNOVSKý, J. Simply impedance measuring system. In Procedings of EEICT 2005 conference. Brno (Czech Republic), 2005, vol. 15, no. 2, p. 56-60.