A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2012, Pages 86-87

  Chan, Chi Hang ^a   Zhu, Yan ^a   Sin, Sai Weng ^a   U, Seng Pan ^a,b   Martins, R P ^a,c  

^a State Key Laboratory of Analog and Mixed Signal VLSI   (Macao)

^b Synopsys Chipidea Microelectronics Macau Limited   (Macao)

^c INSTITUTO SUPERIOR TÉCNICO   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE AREA; HIGH DENSITY; LAYOUT STRUCTURE; LOW-PARASITIC; OFFSET CALIBRATION; ON CHIPS; SAR ADC;

CALIBRATION; VLSI CIRCUITS;

ANALOG TO DIGITAL CONVERSION;

EID: 84866628654     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2012.6243802     Document Type: Conference Paper

References (5)

1. Y.H. Chung, et al., "A 16-mW 8-Bit 1-GS/s Subranging ADC in 55nm CMOS," Symp. VLSI Circuits Dig. Tech. Papers, pp. 128-129, Apr. 2011.
2. T. Yamase, et al., "A 22-mW 7b 1.3G-S/s Pipeline ADC with 1-bit/stage Folding Converter Architecture," Symp. VLSI Circuits Dig. Tech.Papers, pp. 124-125, Apr. 2011.
3. C.H. Chan, et al., "A Reconfigurable Low-Noise Dynamic Comparator with Offset Calibration in 90nm CMOS," IEEE A-SSCC Processings, pp. 233-236, Nov. 2011.
4. W.H. Tu, et al., "A 1.2V 30mW 8b 800MS/s Time-interleaved ADC in 65nm CMOS," Symp. VLSI Circuits Dig. Tech. Papers, pp. 72-73, Nov. 2008.
5. E. Alpman, et al., "A 1.1V 50 mW 2.5 GS/s 7 b time-interleaved C-2C SAR ADC in 45 nm LP digital CMOS," IEEE ISSCC Dig. Tech. Papers, pp. 76-77, Feb. 2009.