Unified solid-state-storage architecture with NAND flash memory and ReRAM that tolerates 32× higher BER for big-data applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 56, Issue , 2013, Pages 226-227

  Tanakamaru, Shuhei ^a,b   Doi, Masafumi ^a   Takeuchi, Ken ^a  

^a CHUO UNIVERSITY   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA-RETENTION; ERROR TOLERANCE; NAND FLASH MEMORY; SOLID-STATE STORAGE;

NAND CIRCUITS;

DIGITAL STORAGE;

EID: 84876562159     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2013.6487711     Document Type: Conference Paper

References (6)

1. Oracle and RAID Usage," http://www.dba-oracle.com/oracle-tips-raid- usage.htm
2. H. Fujii et al., "x11 Performance Increase, x6.9 Endurance Enhancement, 93% Energy Reduction of 3D TSV-Integrated Hybrid ReRAM/MLC NAND SSDs by Data Fragmentation Suppression," IEEE Symp. VLIS Circuits, pp. 134-135, 2012.
3. 64Mbit 50nm ReRAM Prototype," http://www.elpida.com/ja/news/2012/01- 24r.html
4. S. Tanakamaru et al., "95%-Lower-BER 43%-Lower-Power Intelligent Solid-State Drive (SSD) with Asymmetric Coding and Stripe Pattern Elimination Algorithm," ISSCC Dig. Tech. Papers, pp. 204-205, 2011.
5. K. Higuchi et al., "Investigation of Verify-Programming Methods to Achieve 10 Million Cycles for 50nm HfO2 ReRAM," IEEE Int. Memory Workshop, pp.119-122, 2012.
6. S. Tanakamaru et al., "Over-10x-Extended-Lifetime, 76%-Reduced-Error Solid-State Drives (SSDs) with Error-Prediction LDPC Architecture and Error-Recovery Scheme," ISSCC Dig. Tech. Papers, pp. 424-425, 2012.