95%-Lower-BER 43%-lower-power intelligent solid-state drive (SSD) with asymmetric coding and stripe pattern elimination algorithm

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 204-205

  Tanakamaru, Shuhei ^a   Hung, Chinglin ^a   Esumi, Atsushi ^b   Ito, Mitsuyoshi ^b   Li, Kai ^b   Takeuchi, Ken ^a  

^a UNIVERSITY OF TOKYO   (Japan)

^b SIGLEAD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CODES (SYMBOLS); DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC FIELDS; ELECTRIC POWER UTILIZATION; ERROR CORRECTION; MEMORY ARCHITECTURE; NAND CIRCUITS; RANDOM ERRORS; RELIABILITY; SEMICONDUCTOR STORAGE;

ASYMMETRIC CODING; BITLINE CAPACITANCE; ERROR CORRECTING CODE; HIGH RELIABILITY; NAND FLASH MEMORY; RANDOM TELEGRAPH NOISE; SOLID STATE DRIVES; SOLID STATE DRIVES (SSD);

FLASH MEMORY;

EID: 79955726617     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746283     Document Type: Conference Paper

References (8)

1. K. Takeuchi, "NAND successful as a media for SSD," ISSCC, Tutorial T-7, 2008.
2. J. D. Lee et al., "A New Programming Disturbance Phenomenon in NAND Flash Memory by Source/Drain Hot-Electrons Generated by GIDL Current," Non-Volatile Semiconductor Memory Workshop (NVSMW), pp. 31-33, 2006.
3. M. Abraham, "NAND Flash Trends for SSD/Enterprise," Flash Memory Summit, 2010.
4. Y. Y. Tai, "Error Control Coding for MLC Flash Memories," Flash Memory Summit, 2010.
5. K. Takeuchi, "Novel Co-design of NAND Flash Memory and NAND Flash Controller Circuits for sub-30nm Low-Power High-Speed Solid-State Drives (SSD)," S ymposium on VLSI Circuits Dig. Tech. Papers,pp.124-125, 2008.
6. K. Takeuchi et al., "A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories," S ymposium on VLSI Circuits Dig. Tech. Papers,pp.67-68, 1997.
7. C. Lee et al., "A 32Gb MLC NAND-Flash Memory with VTH-Endurance-Enhancing Schemes in 32nm CMOS," ISSCC Dig. Tech. Papers, pp. 446-447, 2010.
8. K. Takeuchi et al., "A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput," ISSCC Dig. Tech. Papers, pp. 144-145, 2006.