Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 56, Issue , 2013, Pages 224-225

  Yu, Hung Chang ^a   Lin, Kai Chun ^a   Lin, Ku Feng ^a   Huang, Chin Yi ^a   Chih, Yu Der ^a   Ong, Tong Chern ^a   Chang, Jonathan ^a   Natarajan, Sreedhar ^a   Tran, Luan C ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CYCLING ENDURANCE; LOW POWER; MAGNETIC TUNNEL JUNCTION; OPTIMIZATION SCHEME; TEST-CHIP; VOLTAGE STRESS; WRITE ENDURANCES; WRITE OPERATIONS;

DYNAMIC RANDOM ACCESS STORAGE; FLASH MEMORY; MRAM DEVICES; STATIC RANDOM ACCESS STORAGE;

MAGNETIC DEVICES;

EID: 84876556756     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2013.6487710     Document Type: Conference Paper

References (3)

1. M. Hosomi, et al., "A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM," IEDM Tech. Dig., pp. 459-462, 2005.
2. K. Miura, et al., "A novel SPRAM (Spin-transfer torque RAM) with synthetic ferrimagnetic free layer for higher immunity to read disturbance and reducing write current dispersion," Symp. VLSI Technology Dig. Tech. Papers, pp. 234-235, 2007.
3. Tai Min, et al., "A Study of Write Margin of Spin Torque Transfer Magnetic Random Access Memory Technology," IEEE Trans. on Magnetics, vol. 46, pp. 2322-2327, 2010.