A 2x25Gb/s deserializer with 2:5 DMUX for 100Gb/s ethernet applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 374-375

  Wu, Ke Chung ^a   Lee, Jri ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

100 GB/S ETHERNET; 100 GBE; BANDWIDTH REQUIREMENT; CMOS DESIGN; COMPONENT COUNT; DESERIALIZERS; INTERNET CONNECTIVITY; MULTI CORE; MULTI-CHANNEL; PHOTONIC INTEGRATIONS; VIRTUALIZATIONS;

MICROPROCESSOR CHIPS;

EID: 77952136534     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433827     Document Type: Conference Paper

References (6)

1. IEEE P802.3ba 40Gb/s and 100Gb/s Ethernet Task Force [Online]. Available: http://www.ieee802.org/3/ba/index.html
2. S. Galal and B. Razavi, "40Gb/s Amplifier and ESD Protection Circuit in 0.18μm CMOS Technology," ISSCC Dig. Tech. Papers, pp. 480-481, Feb. 2004.
3. H. Banba et al., "A CMOS Bandgap Reference Circuit with Sub-1-V Operation," IEEE Journal of Solid-State Circuits, vol. 34, pp. 670-674, May 1999.
4. J. Lee and K.-C. Wu, "A 20Gb/s Full-Rate Linear CDR Circuit with Automatic Frequency Acquisition," ISSCC Dig. Tech. Papers, pp. 366-367, Feb. 2009.
5. K. Kanda et al., "40Gb/s 4:1 MUX/1:4 DEMUX in 90nm standard CMOS," ISSCC Dig. Tech. Papers, pp. 152-153, Feb. 2005.
6. E. Tournier et al., "High-speed dual-modulus prescaler architecture for programmable digital frequency dividers," IEE Electron. Lett., pp. 1433-1434, Nov. 2001.