10:4 MUX and 4:10 DEMUX gearbox LSI for 100-gigabit ethernet link

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 148-149

  Ono, Goichi ^a   Watanabe, Keiki ^a   Muto, Takashi ^a   Yamashita, Hiroki ^a   Fukuda, Koji ^a   Masuda, Noboru ^a   Nemoto, Ryo ^a   Suzuki, Eiichi ^a   Takemoto, Takashi ^a   Yuki, Fumio ^a   Yagyu, Masayoshi ^a   Toyoda, Hidehiro ^a   Kambe, Akihiro ^a   Saito, Tatsuya ^a   Nishimura, Shinji ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BISMUTH ALLOYS; CMOS INTEGRATED CIRCUITS; DEMULTIPLEXING; ELECTRIC POWER UTILIZATION; ETHERNET; IEEE STANDARDS; SI-GE ALLOYS;

65NM CMOS; CMOS TECHNOLOGY; DATA SIGNALS; ETHERNET LINK; PHYSICAL MEDIA DEPENDENTS; SIGE BICMOS; TOTAL POWER CONSUMPTION;

LSI CIRCUITS;

EID: 79955720542     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746258     Document Type: Conference Paper

References (7)

1. IEEE P802.3ba 40 Gb/s and 100 Gb/s Ethernet Task Force; http://grouper.ieee.org/groups/802/3/ba/index.html
2. 100 Gb/s MUX; http://www.semtech.com/images/datasheet/smi10021.pdf
3. 100 Gb/s DEMUX; http://www.semtech.com/images/datasheet/smi10031.pdf
4. K.-C. Wu and J. Lee, "A 2x25Gb/s Deserializer with 2□5 DMUX for 100Gb/s Ethernet Applications," ISSCC Dig. Tech. Papers, pp. 374-375, Feb., 2010.
5. K. Fukuda, H. Yamashita, G. Ono, et al., "A 12.3mW 12.5Gb/s Complete Transceiver in 65nm CMOS," ISSCC Dig. Tech. Papers, pp. 368-369, Feb., 2010.
6. A. Amirkhany, A. Abbasfar, J. Savoj, et al., IEEE Symp. VLSI Circuits, pp. 38- 39, Jun., 2007.
7. N. Nedovic, S. Parikh, A. Kristensson, et al., "A 2x22Gb/s SFI5.2 CDR/Deserializer in 65nm CMOS Technology," IEEE Symp. VLSI Circuits, pp. 10-11, Jun., 2009.