-
1
-
-
0036603490
-
A multiplication-free algorithm and a parellel architecture for affine transformation
-
Badawy, W., Bayoumi, M.: A multiplication-free algorithm and a parellel architecture for affine transformation. J VLSI Signal Process 31, 173-184 (2002).
-
(2002)
J VLSI Signal Process
, vol.31
, pp. 173-184
-
-
Badawy, W.1
Bayoumi, M.2
-
2
-
-
0029350817
-
A multi-ASIC real-time implementation of the two dimensional affine transform with a bilinear interpolation scheme
-
Bentum, M., Samsom, M., Slump, C.: A multi-ASIC real-time implementation of the two dimensional affine transform with a bilinear interpolation scheme. J VLSI Signal Process 10, 261-273 (1995).
-
(1995)
J VLSI Signal Process
, vol.10
, pp. 261-273
-
-
Bentum, M.1
Samsom, M.2
Slump, C.3
-
4
-
-
84874665742
-
An embedded solution of 2D fast affine transform for biomedical imaging systems
-
Bangalore, India
-
Biswal, PK., Banerjee, S.: An embedded solution of 2D fast affine transform for biomedical imaging systems. In: Proceddings of VLSI Design and Test Symposium (VDAT 2009), Bangalore, India, pp. 259-270 (2009).
-
(2009)
Proceddings of VLSI Design and Test Symposium (VDAT 2009)
, pp. 259-270
-
-
Biswal, P.K.1
Banerjee, S.2
-
5
-
-
0030106087
-
Cellular architecture for affine transforms on raster images
-
Biswas, G., Dutta, P., Krishna, P., Sengupta, I.: Cellular architecture for affine transforms on raster images. IEE Proc Comput Digi Tech 143(2), 103-110 (1996).
-
(1996)
IEE Proc Comput Digi Tech
, vol.143
, Issue.2
, pp. 103-110
-
-
Biswas, G.1
Dutta, P.2
Krishna, P.3
Sengupta, I.4
-
6
-
-
72849114564
-
GPU implementation of the affine transform for 3D image registration
-
Crookes, D., Boyle, K., Miller, P., Gillan, C.: GPU implementation of the affine transform for 3D image registration. 13th International Conference on Machine Vision and Image Processing (2009).
-
(2009)
13th International Conference on Machine Vision and Image Processing
-
-
Crookes, D.1
Boyle, K.2
Miller, P.3
Gillan, C.4
-
7
-
-
76649097371
-
An efficient architecture for 3-D discrete wavelet transform
-
Das, A., Hazra, A., Banerjee, S.: An efficient architecture for 3-D discrete wavelet transform. IEEE Trans Circ Syst Video Technol 20(2), 286-296 (2010).
-
(2010)
IEEE Trans Circ Syst Video Technol
, vol.20
, Issue.2
, pp. 286-296
-
-
Das, A.1
Hazra, A.2
Banerjee, S.3
-
8
-
-
0041731791
-
Correction of geometric image distortion using FPGAs
-
Galway, IRL
-
Eadie, D., Shevlin, F., Nisbet, A.: Correction of geometric image distortion using FPGAs. SPIE Conference on Optical Metrology, Imaging, and Machine Vision, Galway, IRL (2002).
-
(2002)
SPIE Conference on Optical Metrology, Imaging, and Machine Vision
-
-
Eadie, D.1
Shevlin, F.2
Nisbet, A.3
-
9
-
-
0024471113
-
Comparison at high spatial frequencies of two-pass and one-pass geometric transformation algorithms
-
Fraser, D.: Comparison at high spatial frequencies of two-pass and one-pass geometric transformation algorithms. Comput Vision Graph Image Process 46, 267-283 (1989).
-
(1989)
Comput Vision Graph Image Process
, vol.46
, pp. 267-283
-
-
Fraser, D.1
-
10
-
-
0038209195
-
VLSI implementation of an efficient ASIC architecture for real time rotation of digital images
-
Ghosh, I., Majumdar, B.: VLSI implementation of an efficient ASIC architecture for real time rotation of digital images. Int J Pattern Recognition Artif Intell 9, 449-462 (1995).
-
(1995)
Int J Pattern Recognition Artif Intell
, vol.9
, pp. 449-462
-
-
Ghosh, I.1
Majumdar, B.2
-
12
-
-
54949138013
-
FPGA implementation of a real-time biologically inspired image enhancement algorithm
-
Iakovidou, C., Vonikakis, V., Andreadis, I.: FPGA implementation of a real-time biologically inspired image enhancement algorithm. J Real-Time Image Process 3, 269-287 (2008).
-
(2008)
J Real-Time Image Process
, vol.3
, pp. 269-287
-
-
Iakovidou, C.1
Vonikakis, V.2
Andreadis, I.3
-
13
-
-
33847331706
-
FPGA implementation of image rotation using modified compensated CORDIC
-
Jiang, XG., Zhou, JY., Shi, JH., Chen, HH.: FPGA implementation of image rotation using modified compensated CORDIC. In: 6th International Conference On ASIC (ASICON 2005), vol. 2, pp. 752-756 (2005).
-
(2005)
6th International Conference On ASIC (ASICON 2005)
, vol.2
, pp. 752-756
-
-
Jiang, X.G.1
Zhou, J.Y.2
Shi, J.H.3
Chen, H.H.4
-
14
-
-
67349226371
-
High performance motion detection: some trends toward new embedded architectures for vision systems
-
Lacassagne, L., Manzanera, A., Denoulet, J., Merigot, A.: High performance motion detection: some trends toward new embedded architectures for vision systems. J Real-Time Image Process 4, 127-146 (2009).
-
(2009)
J Real-Time Image Process
, vol.4
, pp. 127-146
-
-
Lacassagne, L.1
Manzanera, A.2
Denoulet, J.3
Merigot, A.4
-
15
-
-
33749540129
-
-
In: ICIC 2006, Springer, Berlin, Lecture Notes in Computer Science
-
Lee, S., Lee, G., Jang, ES., Kim, WY.: Fast affine transform for real-time machine vision applications. In: ICIC 2006, Springer, Berlin, Lecture Notes in Computer Science 4113, pp. 1180-1190 (2006).
-
(2006)
Fast affine transform for real-time machine vision applications
, vol.4113
, pp. 1180-1190
-
-
Lee, S.1
Lee, G.2
Jang, E.S.3
Kim, W.Y.4
-
16
-
-
37449025677
-
High performance FPGA-based image correlation
-
Lindoso, A., Entrena, L.: High performance FPGA-based image correlation. J Real-Time Image Process 2, 223-233 (2007).
-
(2007)
J Real-Time Image Process
, vol.2
, pp. 223-233
-
-
Lindoso, A.1
Entrena, L.2
-
18
-
-
67650705081
-
Accelerating phase unwrapping and affine transformations for optical quadrature microscopy using CUDA
-
ACM, New York, NY, USA, GPGPU-2
-
Mistry, P., Braganza, S., Kaeli, D., Leeser, M.: Accelerating phase unwrapping and affine transformations for optical quadrature microscopy using CUDA. In: Proceedings of 2nd Workshop on General Purpose Processing on Graphics Processing Units, ACM, New York, NY, USA, GPGPU-2, pp. 28-37 (2009).
-
(2009)
Proceedings of 2nd Workshop on General Purpose Processing on Graphics Processing Units
, pp. 28-37
-
-
Mistry, P.1
Braganza, S.2
Kaeli, D.3
Leeser, M.4
-
20
-
-
79957996258
-
An efficient pass-parallel architecture for embedded block coder in JPEG 2000
-
Sarawadekar, K., Banerjee, S.: An efficient pass-parallel architecture for embedded block coder in JPEG 2000. IEEE Trans Circ Syst Video Technol 21(6), 825-836 (2011).
-
(2011)
IEEE Trans Circ Syst Video Technol
, vol.21
, Issue.6
, pp. 825-836
-
-
Sarawadekar, K.1
Banerjee, S.2
-
21
-
-
85032752133
-
A survey of medical image registration on multicore and the GPU
-
Shams, R., Sadeghi, P., Kennedy, R., Hartley, R.: A survey of medical image registration on multicore and the GPU. IEEE Signal Process Mag 27(2), 50-60 (2010).
-
(2010)
IEEE Signal Process Mag
, vol.27
, Issue.2
, pp. 50-60
-
-
Shams, R.1
Sadeghi, P.2
Kennedy, R.3
Hartley, R.4
-
23
-
-
33751550908
-
Accelerating rotation of high-resolution images
-
Suchitra, S., Lam, S., Clarke, C., Srikanthan, T.: Accelerating rotation of high-resolution images. IEE Proc Vision Image Signal Process 153(6), 815-824 (2006).
-
(2006)
IEE Proc Vision Image Signal Process
, vol.153
, Issue.6
, pp. 815-824
-
-
Suchitra, S.1
Lam, S.2
Clarke, C.3
Srikanthan, T.4
-
24
-
-
0023330705
-
Hardware for image rotation by twice skew transformations
-
Tsuchida, N., Yamada, Y., Ueda, M.: Hardware for image rotation by twice skew transformations. IEEE Trans Acoustics Speech Signal Process 35(4), 527-532 (1987).
-
(1987)
IEEE Trans Acoustics Speech Signal Process
, vol.35
, Issue.4
, pp. 527-532
-
-
Tsuchida, N.1
Yamada, Y.2
Ueda, M.3
-
25
-
-
0029392117
-
Convolution based interpolation for fast, high quality rotation of images
-
Unser, M., Thevenaz, P., Yaroslavsky, L.: Convolution based interpolation for fast, high quality rotation of images. IEEE Trans Image Process 10(4), 1371-1381 (1995).
-
(1995)
IEEE Trans Image Process
, vol.10
, Issue.4
, pp. 1371-1381
-
-
Unser, M.1
Thevenaz, P.2
Yaroslavsky, L.3
|