An Efficient pass-parallel architecture for embedded block coder in JPEG 2000

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 21, Issue 6, 2011, Pages 825-836

  Sarawadekar, Kishor ^a   Banerjee, Swapna ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY   (India)

Author keywords

Embedded block coding with optimized truncation (EBCOT); field programmable gate array (FPGA); JPEG 2000; MQ coder; VLSI architecture

Indexed keywords

BIT PLANE CODER; COMPRESSION SYSTEM; DIGITAL CINEMAS; EBCOT ARCHITECTURE; EMBEDDED BLOCK CODING WITH OPTIMIZED TRUNCATION; EMBEDDED BLOCKS; FIELD PROGRAMMABLE GATE ARRAY PLATFORM; HIGH THROUGHPUT; HIGH-DEFINITION TV; HIGH-SPEED; JPEG 2000; MATRIX; MQ-CODER; PASS-PARALLEL ARCHITECTURES; PROPOSED ARCHITECTURES; QUANTIZERS; REAL-TIME IMAGE COMPRESSION; RENORMALIZATION; VLSI ARCHITECTURE;

DECODING; ENCODING (SYMBOLS); FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; IMAGE CODING; IMAGE COMPRESSION; LOGIC GATES; MAPPING; MAPS; OPTIMIZATION; PARALLEL ARCHITECTURES; SATELLITE IMAGERY; SIGNAL ENCODING; THROUGHPUT;

MEDICAL IMAGING;

EID: 79957996258     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSVT.2011.2133450     Document Type: Article

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