Complexity-reducing algorithm for serial scheduled min-sum decoding of LDPC codes

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E92-A, Issue 10, 2009, Pages 2411-2417

  Uchikawa, Hironori ^a   Harada, Kohsuke ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

Complexity; Low density parity check codes; Min sum decoding; Serial scheduling

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; ERROR CORRECTION; ITERATIVE METHODS;

CHECK NODES; COMPLEXITY; CORRECTION PERFORMANCE; DECODING COMPLEXITY; LOG LIKELIHOOD RATIOS (LLR); LOW-DENSITY PARITY-CHECK (LDPC) CODES; MIN-SUM DECODING; SERIAL SCHEDULING;

DECODING;

EID: 84872794735     PISSN: 09168508     EISSN: 17451337     Source Type: Journal    
DOI: 10.1587/transfun.E92.A.2411     Document Type: Article

References (14)

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