High-throughput decoder for low-density parity-check code

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2006, Issue , 2006, Pages 112-113

  Ishikawa, Tatsuyuki ^a   Shimizu, Kazunori ^a   Ikenaga, Takeshi ^a   Goto, Satoshi ^a  

^a WASEDA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; DECODING; MICROPROCESSOR CHIPS; NATURAL FREQUENCIES; THROUGHPUT;

DECODER CHIPS; HIGH THROUGHPUT DECODER; LOW DENSITY PARITY CHECK CODE(LDPC); METAL LAYER CMOS TECHNOLOGY;

CODES (SYMBOLS);

EID: 33748611888     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118332     Document Type: Conference Paper

References (2)

1. M. M. Mansour, N. R. Shanbhag, "Low-power VLSI decoder architectures for LDPC codes," Proceedings of the 2002 International Symposium on Low Power Electronics and Design, pp.284-289, 2002.
2. M. Karkooti, J. R. Cavallaro, "Semi-Parallel Reconfigurable Architecutures for Real-Time LDPC Decoding," Proceeding 2004 IEEE International Conference on Information Technology, ITCC'04, Volume1, pp.579-585, 2004.