A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10-19

European Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 527-530

  Okumura, Shunsuke ^a   Yoshimoto, Shusuke ^a   Kawaguchi, Hiroshi ^a   Yoshimoto, Masahiko ^a,b  

^a KOBE UNIVERSITY   (Japan)

^b JAPAN SCIENCE AND TECHNOLOGY AGENCY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BITLINES; FAILURE RATE; LOAD TRANSISTORS; RANDOM VARIATION; ROOM TEMPERATURE; SMALL AREA; SUPPLY VOLTAGES; TEST CHIPS; TRANSISTOR CHARACTERISTICS; WRITE OPERATIONS;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 82955241415     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2011.6044938     Document Type: Conference Paper

References (12)

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