A stochastic reconfigurable architecture for fault-tolerant computation with sequential logic

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2012, Pages 303-308

  Li, Peng ^a   Qian, Weikang ^b   Lilja, David J ^a  

^a University of Minnesota   (United States)

^b SHANGHAI JIAO TONG UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

BIT STREAM; CLOCK FREQUENCY; COMPLEX ARITHMETIC; COMPUTING TECHNIQUES; FAULT-TOLERANT COMPUTATION; PARALLEL PROCESSING; PROCESSING TIME; SEQUENTIAL LOGIC; SOFT ERROR;

FAULT TOLERANCE; RECONFIGURABLE ARCHITECTURES;

STOCHASTIC SYSTEMS;

EID: 84872059783     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2012.6378656     Document Type: Conference Paper

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