BTL: A framework for measuring and modeling energy in memory hierarchies

Proceedings - Symposium on Computer Architecture and High Performance Computing

Volumn , Issue , 2012, Pages 139-146

  Manousakis, Ioannis ^a   Nikolopoulos, Dimitrios S ^b  

^a INSTITUTE OF COMPUTER SCIENCE   (Greece)

^b QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

Energy; Energy Efficiency; Memory; Power; Power Modeling

Indexed keywords

BOTTOM LINES; COMPUTING SYSTEM; DYNAMIC ENERGY CONSUMPTION; ENERGY; ENERGY AWARE; ENERGY CONSUMER; ENERGY OPTIMIZATION; HIGH DENSITY; LOWER BOUNDS; MEMORY ACCESS PATTERNS; MEMORY HIERARCHY; MEMORY SUBSYSTEMS; MICRO-BENCHMARK; MULTIPLE LEVELS; POWER; POWER MODELING; PROCESSOR SPEED;

DATA STORAGE EQUIPMENT; DATA TRANSFER; DYNAMIC RANDOM ACCESS STORAGE; ENERGY EFFICIENCY; ENERGY UTILIZATION; MEMORY ARCHITECTURE; OPTIMIZATION;

COMPUTER SYSTEMS;

EID: 84871656418     PISSN: 15506533     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBAC-PAD.2012.38     Document Type: Conference Paper

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