Graphics processing unit (GPU) programming strategies and trends in GPU computing

Journal of Parallel and Distributed Computing

Volumn 73, Issue 1, 2013, Pages 4-13

  Brodtkorb, André R ^a   Hagen, Trond R ^a,b   Sætra, Martin L ^b  

^a SINTEF ICT   (Norway)

^b UNIVERSITY OF OSLO   (Norway)

Author keywords

Debugging; Future trends; GPU computing; Hardware; Heterogeneous computing; Optimization; Profiling

Indexed keywords

FUTURE TRENDS; GPU COMPUTING; GPU PROGRAMMING; GRAPHICS PROCESSING UNIT; GRAPHICS PROCESSING UNITS; HETEROGENEOUS COMPUTING; PROFILING; PROOF OF CONCEPT;

COMPUTER DEBUGGING; COMPUTER GRAPHICS; COMPUTER HARDWARE; HARDWARE; INDUSTRIAL APPLICATIONS; OPTIMIZATION; PROGRAM PROCESSORS;

COMPUTER GRAPHICS EQUIPMENT;

EID: 84869502554     PISSN: 07437315     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.jpdc.2012.04.003     Document Type: Article

References (24)

1. Advanced micro devices, AMD Fusion family of APUs: enabling a superior, immersive PC experience, Technical report, 2010.
2. G.M. Amdahl Validity of the Single Processor Approach to Achieving Large Scale Computing Capabilities 2000 Morgan Kaufmann Publishers Inc. San Francisco, CA, USA pp. 79-81 (Chapter 2)
3. K. Asanovic, R. Bodik, B. Catanzaro, J. Gebis, P. Husbands, K. Keutzer, D. Patterson, W. Plishker, J. Shalf, S. Williams, K. Yelick, The landscape of parallel computing research: a view from Berkeley, Technical report, EECS Department, University of California, Berkeley, December 2006.
4. A.R. Brodtkorb, C. Dyken, T.R. Hagen, J.M. Hjelmervik, and O. Storaasli State-of-the-art in heterogeneous computing Scientific Programming 18 1 2010 1 33
5. A.R. Brodtkorb, M.L. Sætra, and M. Altinakar Efficient shallow water simulations on GPUs: implementation, visualization, verification, and validation Computers & Fluids 55 0 2012 1 12
6. A. Davidson, J.D. Owens, Toward techniques for auto-tuning GPU algorithms, in: Proceedings of Para 2010: State of the Art in Scientific and Parallel Computing, 2010.
7. M. Harris, NVIDIA GPU computing SDK 4.1: optimizing parallel reduction in CUDA, 2011.
8. M. Harris, and D. Göddeke General-purpose computation on graphics hardware http://gpgpu.org
9. Intel, Intel many integrated core (Intel MIC) architecture: ISC'11 demos and performance description, Technical report, 2011.
10. Intel Labs, The SCC platform overview, Technical report, Intel Corporation, 2010.
11. D.E. Knuth Structured programming with go to statements Computing Surveys 6 1974 261 301
12. Y. Li, J. Dongarra, S. Tomov, A note on auto-tuning gemm for GPUs, in: Proceedings of the 9th International Conference on Computational Science: Part I, 2009.
13. J.D.C. Little, and S.C. Graves Building Intuition: Insights from Basic Operations Management Models and Principles 2008 Springer pp. 81-100 (Chapter 5)
14. D.T. Marr, F. Binns, D.L. Hill, G. Hinton, D.A. Koufaty, J.A. Miller, and M. Upton Hyper-threading technology architecture and microarchitecture Intel Technology Journal 6 1 2002 1 12
15. P. Micikevicius, Analysis-driven performance optimization, [Conference presentation], 2010 GPU Technology Conference, Session 2012, 2010.
16. P. Micikevicius, Fundamental performance optimizations for GPUs, [Conference presentation], 2010 GPU Technology Conference, session 2011, 2010.
17. NVIDIA, NVIDIA's next generation CUDA compute architecture: Fermi, 2010.
18. NVIDIA, NVIDIA CUDA programming guide 4.1, 2011.
19. NVIDIA, NVIDIA GeForce GTX680, Technical report, NVIDIA Corporation, 2012.
20. J. Owens, M. Houston, D. Luebke, S. Green, J. Stone, and J. Phillips GPU computing Proceedings of the IEEE 96 5 2008 879 899
21. L. Seiler, D. Carmean, E. Sprangle, T. Forsyth, M. Abrash, P. Dubey, S. Junkins, A. Lake, J. Sugerman, R. Cavin, R. Espasa, E. Grochowski, T. Juan, and P. Hanrahan Larrabee: a many-core x86 architecture for visual computing ACM Transactions on Graphics 27 3 2008 18:1 18:15
22. G. Taylor, Energy efficient circuit design and the future of power delivery, [Conference presentation], Electrical Performance of Electronic Packaging and Systems, October 2009.
23. Top 500 supercomputer sites, http://www.top500.org/, November 2011.
24. S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar An 80-tile sub-100-w teraflops processor in 65-nm CMOS Solid-State Circuits 43 1 2008 29 41