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Volumn , Issue , 2012, Pages 496-500

A novel CORDIC based unified architecture for DCT and IDCT

Author keywords

CORDIC; DCT IDCT; FPGA implementation; Unified architecture

Indexed keywords

CORDIC; DCT ALGORITHMS; DCT/IDCT; DEVELOPMENT COSTS; FPGA IMPLEMENTATIONS; MATRIX DECOMPOSITION; UNIFIED ARCHITECTURE; VERILOG;

EID: 84869200785     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICoOM.2012.6316324     Document Type: Conference Paper
Times cited : (10)

References (8)
  • 2
    • 34249773988 scopus 로고    scopus 로고
    • An efficient unified framework for implementation of a prime-length DCT/IDCT with high throughput
    • Doru-Florin Chiper, M. N. S. Swamy, M. Omair Ahmad, An Efficient Unified Framework for Implementation of a Prime-Length DCT/IDCT With High Throughput, IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL. 55, NO. 6, 2926-2936, 2007.
    • (2007) IEEE Transactions on Signal Processing , vol.55 , Issue.6 , pp. 2926-2936
    • Chiper, D.-F.1    Swamy, M.N.S.2    Omair Ahmad, M.3
  • 3
    • 0031118127 scopus 로고    scopus 로고
    • Unified systolic arrays for computation of DCT/DST/DHT
    • Apr
    • S. B. Pan and R.-H. Park, "Unified systolic arrays for computation of DCT/DST/DHT, " IEEE Trans. Circuits Syst. Video Technol., vol. 7, no. 2, pp. 413-419, Apr. 1997.
    • (1997) IEEE Trans. Circuits Syst. Video Technol. , vol.7 , Issue.2 , pp. 413-419
    • Pan, S.B.1    Park, R.-H.2
  • 4
    • 38649114668 scopus 로고    scopus 로고
    • Low-power and high quality CORDIC-based loeffler DCT for signal processing
    • C.-C.Sun, S.-J.Ruan, B.Heyne, J.Goetze, Low-power and high quality CORDIC-based Loeffler DCT for signal processing, IET Proc.-Circuits, Devices & Systems, vol. 1, no. 6, (2007) pp. 453-461.
    • (2007) IET Proc.-Circuits, Devices & Systems , vol.1 , Issue.6 , pp. 453-461
    • Sun, C.-C.1    Ruan, S.-J.2    Heyne, B.3    Goetze, J.4
  • 7
    • 0036173699 scopus 로고    scopus 로고
    • A scaled DCT architecture with the CORDIC algorithm
    • S. Yu, E. E. Swartzlander, A scaled DCT architecture with the CORDIC algorithm, IEEE Trans. Signal Processing, vol. 50, no. 1, (2002) pp. 160-167.
    • (2002) IEEE Trans. Signal Processing , vol.50 , Issue.1 , pp. 160-167
    • Yu, S.1    Swartzlander, E.E.2
  • 8
    • 1942519780 scopus 로고    scopus 로고
    • Low-power multiplierless DCT architecture using image data correlation
    • H. Jeong, J. Kim, W. K. Cho, Low-power multiplierless DCT architecture using image data correlation, IEEE Trans. Consumer Electronics, No.1, vol.50, (2004), pp.262-267.
    • (2004) IEEE Trans. Consumer Electronics , vol.50 , Issue.1 , pp. 262-267
    • Jeong, H.1    Kim, J.2    Cho, W.K.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.