Efficient cycle-accurate simulation of the UltraSPARC III CPU

Conferences in Research and Practice in Information Technology Series

Volumn 62, Issue , 2007, Pages 221-228

  Strazdins, Peter ^a   Clarke, Bill ^a   Over, Andrew ^a  

^a AUSTRALIAN NATIONAL UNIVERSITY   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

CYCLE-ACCURATE SIMULATION; MICRO ARCHITECTURES; NOVEL TECHNIQUES; PERFORMANCE LOSS; SIMULATION SPEED; SUPERSCALAR PROCESSOR; ULTRASPARC;

COMPUTER ARCHITECTURE;

PROGRAM PROCESSORS;

EID: 84868699931     PISSN: 14451336     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

1. Australian National University (n.d.), 'The CCNUMA project: Computational Chemistry on Non-Uniform Memory-access Architectures', http://cs.anu.edu.au/CC- NUMA.*http://cs.anu.edu.au/CC-NUMA
2. Bedichek, R. C. (1995), Talisman: Fast and Accurate Multicomputer Simulation, in 'Proceedings of the 1995 ACM SIGMETRICS Joint Internatiional Conference on Measurement and Modelling of Computer Systems', ACM Press, pp. 14-24.
3. Bose, P. & Conbte, T. M. (1998), 'Performance Analysis and its Impact on Design', IEEE Computer pp. 41-49. (Pubitemid 128556566)
4. Burger, D. & Austin, T. (1997), The SimpleScalar Tool Set, Version 2.0, Technical Report TR-1342, University of Wisconsin-Madison Computer Sciences Department.
5. Clarke, B., Czezowski, A. & Strazdins, P. (2002), Implementation aspects of a SPARC V9 complete machine simulator, in M. Oudshoorn, ed., 'Computer Science 2002', Vol. 4 of Conferences in Research and Practice in Information Technology, Australian Computer Society, Monash University, Melbourne, pp. 23-32.
6. Gibson, J., Kunz, R., Ofelt, D., Horowitz, M., Hennessy, J. & Heinrich, M. (2000), FLASH vs. (Simulated) FLASH: Closing the Simulation Loop, in 'Proceedings of the Ninth International Conference on Architectural Support for Programming Languages and Operating Systems', ACM Press, pp. 49-58. (Pubitemid 32470886)
7. Kumar, R., Tullsen, D. M., Jouppi, N. P. & Ranganthan, P. (2005), 'Heterogenous Chip Multiprocessors', IEEE Computer 38(11), 32-38.
8. Loh, G. (2001), A Time-Stamping Algorithm for Efficient Performance Estimation of Superscalar Processors, in 'Proceedings of the 2001 ACM SIGMETRICS Joint Internatiional Conference on Measurement and Modelling of Computer Systems', ACM Press, pp. 72-81. (Pubitemid 32865924)
9. NASA Advanced Supercomputing (n.d.), 'NAS Parallel Benchmarks', http://www.nas.nasa.gov/Software/NPB/.Version3.1.*http://www.nas.nasa.gov/ Software/NPB/
10. Nussbaum, D., Fedorova, A. & Small, C. (2004), An overview of the Sam CMT simulator kit, Technical Report TR-2004-133, Sun Microsystems Research Labs. *http://research.sun.com/techrep/2004/abstract-133.html
11. Over, A., Strazdins, P. & Clarke, B. (2005), Cycle-Accurate Memory Modelling: A Case-Study in Validation, in 'Proceedings of the 13th International Symposium on Modelling, Analysis and Simulation of Computer and Telcommunication Systems', IEEE, pp. 85-94. (Pubitemid 43791013)
12. Pai, V. S., Ranganathan, P. & Adve, S. V. (1997), RSIM: An Execution-Driven Simulator for ILP-Based Shared-Memory Multiprocessors and Uniprocessors, in 'Proceedings of the Third Workshop on Computer Architecture Education'. Also appears in IEEE TCCA Newsletter, October 1997.
13. Rosenblum, M., Bugnion, E., Devine, S. & Herrod, S. (1997), 'Using the SimOS Machine Simulator to Study Complex Computer Systems', ACM TOMACS Special Issue on Computer Simulation
14. Schnarr, E. C., Hill, M. D. & Larus, J. R. (2001), Facile: a language and compiler for highperformance processor simulators, in 'PLDI '01: Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation', ACM Press, pp. 321-331.
15. Schnarr, E. & Larus, J. R. (1998), Fast out-of-order processor simulation using memoization, in 'Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems', ACM Press, New York, New York, pp. 283-294.
16. Strazdins, P. (2005), CycleCounter: an Efficient and Accurate UltraSPARC III CPU Simulation Module, Technical Report TR-CS-05-01, Department of Computer Science, Australian National University.
17. Sun (2002), UltraSPARC III Cu User's Manual.
18. Virtutech (n.d.), 'Simics 1.0', http://www.simics.com/.s*http:// www.simics.com/