Efficient hardware implementation of threshold neural networks

2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012

Volumn , Issue , 2012, Pages 1-4

  Zamanlooy, Babak ^a   Mirhassani, Mitra ^a  

^a UNIVERSITY OF WINDSOR   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVATION FUNCTIONS; CMOS PROCESSS; EFFICIENT ARCHITECTURE; EXTREME LEARNING MACHINE; HARDWARE IMPLEMENTATIONS; HYPERBOLIC TANGENT; MATHEMATICAL DERIVATION; NETWORK TRAINING; NOISE-TO-SIGNAL RATIOS; OPTIMUM NUMBER; PERFORMANCE METRICES; PROPOSED ARCHITECTURES; THRESHOLD NETWORKS; VLSI IMPLEMENTATION;

CMOS INTEGRATED CIRCUITS; LEARNING ALGORITHMS; NETWORK ARCHITECTURE; NEURAL NETWORKS; VLSI CIRCUITS;

HARDWARE;

EID: 84868267616     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NEWCAS.2012.6328941     Document Type: Conference Paper

References (11)

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