Formation of a top electrode on vertical Si nanowire devices using graphene as a supporting layer

Applied Physics Express

Volumn 5, Issue 10, 2012, Pages

  Jeong, Hyeon Ho ^a   Kim, Jungkil ^b,c   Lee, Jinsup ^a   Jeon, Seokwoo ^a   Lee, Woo ^b,c   Lee, Seok Hee ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b Korea Research Institute of Standards and Science   (South Korea)

^c University of Science and Technology (UST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

AIR GAP STRUCTURES; DEVICE INTEGRATION; MATERIAL PROPERTY; METAL DEPOSITION; NANOWIRE DEVICES; SELF-ALIGNED; SHALLOW-TRENCH-ISOLATION PROCESS; SI NANOWIRE; SILICON NANOWIRE ARRAYS; SILICON NANOWIRES; TOP-DOWN APPROACH;

GRAPHENE;

NANOWIRES;

EID: 84868159295     PISSN: 18820778     EISSN: 18820786     Source Type: Journal    
DOI: 10.1143/APEX.5.105103     Document Type: Article

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