-
1
-
-
0030716608
-
Datascalar architectures
-
Denver, Colorado, 2-4 June . ACM SIGARCH and IEEE Computer Society TCCA
-
Doug Burger, Stefanos Kaxiras, and James R. Goodman. DataScalar architectures. In Proceedings of the 24th Annual International Symposium on Computer Architecture (ISCA '97), Denver, Colorado, 2-4 June 1997. ACM SIGARCH and IEEE Computer Society TCCA. ftp://ftp. cs. wisc. edu/galileo/papers/ISCA97 ds. ps.
-
(1997)
Proceedings of the 24th Annual International Symposium on Computer Architecture (ISCA '97)
-
-
Burger, D.1
Kaxiras, S.2
Goodman, J.R.3
-
2
-
-
0004116989
-
Introduction to algorithms
-
MIT Press, Cambridge, MA
-
Thomas H. Cormen, Charles E. Leiserson, and Ronald L. Rivest. Introduction to Algorithms. The MIT Electrical Engineering and Computer Science Series. MIT Press, Cambridge, MA, 1990.
-
(1990)
The mit Electrical Engineering and Computer Science Series
-
-
Cormen, T.H.1
Leiserson, C.E.2
Rivest, R.L.3
-
4
-
-
0032069449
-
Issue logic for a 600-mhz out-of-order execution microprocessor
-
May
-
James A. Farrell and Timothy C. Fischer. Issue logic for a 600-mhz out-of-order execution microprocessor. IEEE Journal of Solid-State Circuits, 33(5):707-712, May 1998.
-
(1998)
IEEE Journal of Solid-State Circuits
, vol.33
, Issue.5
, pp. 707-712
-
-
Farrell, J.A.1
Fischer, T.C.2
-
7
-
-
84950141521
-
-
Ultrascalar Memo 1, Yale University, 51 Prospect Street, New Haven, CT 06525, November
-
Dana S. Henry and Bradley C. Kuszmaul. Cyclic segmented parallel prefix. Ultrascalar Memo 1, Yale University, 51 Prospect Street, New Haven, CT 06525, November 1998. http://ee. yale. edu/papers/usmemo1. ps. gz.
-
(1998)
Cyclic Segmented Parallel Prefix
-
-
Henry, D.S.1
Kuszmaul, B.C.2
-
8
-
-
85037068790
-
-
Ultrascalar Memo 2, Yale University, 51 Prospect Street, New Haven, CT 06525, 23 November
-
Dana S. Henry and Bradley C. Kuszmaul. An efficient, prioritized scheduler using cyclic prefix. Ultrascalar Memo 2, Yale University, 51 Prospect Street, New Haven, CT 06525, 23 November 1998. http://ee. yale. edu/papers/usmemo2. ps. gz.
-
(1998)
An Efficient, Prioritized Scheduler Using Cyclic Prefix
-
-
Henry, D.S.1
Kuszmaul, B.C.2
-
9
-
-
0027883469
-
Limits of control flow on parallelism
-
Gold Coast, Australia, May 1992. ACM SIGARCH Computer Architecture News
-
Monica S. Lam and Robert P. Wilson. Limits of control flow on parallelism. In The 19th Annual International Symposium on Computer Architecture (ISCA '92), pages 46-57, Gold Coast, Australia, May 1992. ACM SIGARCH Computer Architecture News, Volume 20, Number 2.
-
The 19th Annual International Symposium on Computer Architecture (ISCA '92)
, vol.20
, Issue.2
, pp. 46-57
-
-
Lam, M.S.1
Wilson, R.P.2
-
10
-
-
16144366475
-
The network architecture of the connection machine cm-5
-
C. E. Leiserson, Z. S. Abuhamdeh, D. C. Douglas, C. R. Feynman, M. N. Ganmukhi, J. V. Hill, W. D. Hillis, B. C. Kuszmaul, M. A. St. Pierre, D. S. Wells, M. C. Wong, S.-W. Yang, and R. Zak. The network architecture of the Connection Machine CM-5. Journal of Parallel and Distributed Computing, 33(2):145-158, 1996. ftp://theory. lcs. mit. edu/pub/bradley/jpdc96. ps. Z.
-
(1996)
Journal of Parallel and Distributed Computing
, vol.33
, Issue.2
, pp. 145-158
-
-
Leiserson, C.E.1
Abuhamdeh, Z.S.2
Douglas, D.C.3
Feynman, C.R.4
Ganmukhi, M.N.5
Hill, J.V.6
Hillis, W.D.7
Kuszmaul, B.C.8
Pierre, S.M.A.9
Wells, D.S.10
Wong, M.C.11
Yang, S.-W.12
Zak, R.13
-
11
-
-
0022141776
-
Fat-trees: Universal networks for hardware-efficient supercomputing
-
October
-
Charles E. Leiserson. Fat-trees: Universal networks for hardware-efficient supercomputing. IEEE Transactions on Computers, C-34(10):892-901, October 1985.
-
(1985)
IEEE Transactions on Computers
, vol.C-34
, Issue.10
, pp. 892-901
-
-
Leiserson, C.E.1
-
12
-
-
0021218308
-
Magic: A VLSI layout system
-
Los Angeles, CA, USA, June . IEEE Computer Society Press
-
J. K. Ousterhout, G. T. Hamachi, R. N. Mayo, W. S. Scott, and G. S. Taylor. Magic: A VLSI layout system. In ACM IEEE 21st Design Automation Conference, pages 152-159, Los Angeles, CA, USA, June 1984. IEEE Computer Society Press.
-
(1984)
ACM IEEE 21st Design Automation Conference
, pp. 152-159
-
-
Ousterhout, J.K.1
Hamachi, G.T.2
Mayo, R.N.3
Scott, W.S.4
Taylor, G.S.5
-
13
-
-
0030676681
-
Complexity-effective superscalar processors
-
Denver, Colorado, 2-4 June . ACM SIGARCH and IEEE Computer Society TCCA. See also [14]
-
Subbarao Palacharla, Norman P. Jouppi, and J. E. Smith. Complexity-effective superscalar processors. In Proceedings of the 24th Annual International Symposium on Computer Architecture (ISCA '97), pages 206-218, Denver, Colorado, 2-4 June 1997. ACM SIGARCH and IEEE Computer Society TCCA. http:// www. ece. wisc. edu/jes/papers/isca. ss. ps. See also [14].
-
(1997)
Proceedings of the 24th Annual International Symposium on Computer Architecture (ISCA '97)
, pp. 206-218
-
-
Palacharla, S.1
Jouppi, N.P.2
Smith, J.E.3
-
14
-
-
0003926726
-
Quantifying the complexity of superscalar processors
-
University of Wisconsin, Madison, 19 November
-
Subbarao Palacharla, Norman P. Jouppi, and James E. Smith. Quantifying the complexity of superscalar processors. Technical Report CS-TR-96-1328, University of Wisconsin, Madison, 19 November 1996. ftp:// ftp. cs. wisc. edu/sohi/complexity. report. ps. Z.
-
(1996)
Technical Report CS-TR-96-1328
-
-
Palacharla, S.1
Jouppi, N.P.2
Smith, J.E.3
-
15
-
-
0031594002
-
Improving trace cache effectiveness with branch promotion and trace packing
-
Barcelona, Spain, 27 June-1 July 1998. IEEE Computer Society TCCA and ACM SIGARCH, IEEE Computer Society, Los Alamitos, CA, published as Computer Architecture News June
-
Sanjay Jeram Patel, Marius Evers, and Yale N. Patt. Improving trace cache effectiveness with branch promotion and trace packing. In Proceedings of the 25th Annual International Symposium on Computer Architecture, pages 262-271, Barcelona, Spain, 27 June-1 July 1998. IEEE Computer Society TCCA and ACM SIGARCH, IEEE Computer Society, Los Alamitos, CA, published as Computer Architecture News, 26(3), June 1998. http: //www. eecs. umich. edu/HPS/pub/promotion isca25. ps.
-
(1998)
Proceedings of the 25th Annual International Symposium on Computer Architecture
, vol.26
, Issue.3
, pp. 262-271
-
-
Jeram Patel, S.1
Evers, M.2
Patt, Y.N.3
-
16
-
-
0031235595
-
One billion transistors, one uniprocessor, one chip
-
September
-
Yale N. Patt, Sanjay J. Patel, Marius Evers, Daniel H. Friendly, and Jared Stark. One billion transistors, one uniprocessor, one chip. Computer, 30(9):51-57, September 1997. http://www. computer. org/computer/ co1997/r9051abs. htm.
-
(1997)
Computer
, vol.30
, Issue.9
, pp. 51-57
-
-
Patt, Y.N.1
Patel, S.J.2
Evers, M.3
Friendly, D.H.4
Stark, J.5
-
17
-
-
0030380559
-
Trace cache: A low latency approach to high bandwidth instruction fetching
-
Paris, France, 2-4 December . IEEE Computer Society TC-MICRO and ACMSIGMICRO
-
Eric Rotenberg, Steve Bennett, and James E. Smith. Trace cache: A low latency approach to high bandwidth instruction fetching. In Proceedings of the 29th Annual International Symposium on Microarchitecture (MICRO 29), pages 24-34, Paris, France, 2-4 December 1996. IEEE Computer Society TC-MICRO and ACMSIGMICRO. http://www. cs. wisc. edu/ericro/TC micro29. ps.
-
(1996)
Proceedings of the 29th Annual International Symposium on Microarchitecture (MICRO 29)
, pp. 24-34
-
-
Rotenberg, E.1
Bennett, S.2
Smith, J.E.3
-
18
-
-
0017922490
-
The CRAY-1 computer system
-
January
-
Richard M. Russell. The CRAY-1 computer system. Communications of the ACM, 21(1):63-72, January 1978.
-
(1978)
Communications of the ACM
, vol.21
, Issue.1
, pp. 63-72
-
-
Russell, R.M.1
-
19
-
-
0029182711
-
Multiscalar processors
-
Santa Margherita Ligure, Italy, 22-24 June . ACMSIGARCH and IEEE Computer Society TCCA. Computer Architecture News, May 1994
-
Gurindar S. Sohi, Scott E. Breach, and T. N. Vijaykumar. Multiscalar processors. In Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA '95), pages 414-425, Santa Margherita Ligure, Italy, 22-24 June 1995. ACMSIGARCH and IEEE Computer Society TCCA. Computer Architecture News, 23(2), May 1994.
-
(1995)
Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA '95)
, vol.23
, Issue.2
, pp. 414-425
-
-
Sohi, G.S.1
Breach, S.E.2
Vijaykumar, T.N.3
-
20
-
-
0002499329
-
The counterflow pipeline processor architecture
-
Fall
-
Robert F. Sproull, Ivan E. Sutherland, and Charles E. Molnar. The counterflow pipeline processor architecture. IEEE Design & Test of Computers, 11(3):48-59, Fall 1994.
-
(1994)
IEEE Design & Test of Computers
, vol.11
, Issue.3
, pp. 48-59
-
-
Sproull, R.F.1
Sutherland, I.E.2
Molnar, C.E.3
-
22
-
-
0020886345
-
The VLSI complexity of sorting
-
December
-
Clark D. Thompson. The VLSI complexity of sorting. IEEE Transactions on Computers, C-32:1171-1184, December 1983.
-
(1983)
IEEE Transactions on Computers
, vol.C-32
, pp. 1171-1184
-
-
Thompson, C.D.1
-
24
-
-
84969344997
-
Increasing the instruction fetch rate via multiple branch prediction and a branch address cache
-
Tokyo, Japan, 20-22 July . ACM SIGARCH
-
T.-Y. Yeh, D. T. Marr, and Y. N. Patt. Increasing the instruction fetch rate via multiple branch prediction and a branch address cache. In Conference Proceedings, 1993 International Conference on Supercomputing, pages 67-76, Tokyo, Japan, 20-22 July 1993. ACM SIGARCH.
-
(1993)
Conference Proceedings, 1993 International Conference on Supercomputing
, pp. 67-76
-
-
Yeh, T.-Y.1
Marr, D.T.2
Patt, Y.N.3
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