Investigating memory optimization of hash-index for next generation sequencing on multi-core architecture

Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012

Volumn , Issue , 2012, Pages 665-674

  Wang, Wendi ^a,b   Tang, Wen ^a,b   Li, Linchuan ^a,b   Tan, Guangming ^a   Zhang, Peiheng ^a   Sun, Ninghui ^a  

^a INSTITUTE OF GEOLOGY AND GEOPHYSICS   (China)

^b UNIVERSITY OF CHINESE ACADEMY OF SCIENCES   (China)

Author keywords

memory optimization; next generation sequencing

Indexed keywords

COMPUTING SYSTEM; DATA LOCALITY; DATA-INTENSIVE COMPUTATION; INDEX BASED ALGORITHM; INDEX COMPRESSION; MEMORY OPTIMIZATION; MULTICORE ARCHITECTURES; MULTIPLE THREADS; NEXT-GENERATION SEQUENCING; OPTIMIZATION APPROACH; ORIGINAL ALGORITHMS; QUERY PERFORMANCE; SEQUENTIAL ACCESS; SHARED CACHE; SHORT SEQUENCES;

DISTRIBUTED PARAMETER NETWORKS; MICROPROCESSOR CHIPS; OPTIMIZATION; PARALLEL ALGORITHMS; PARALLEL ARCHITECTURES;

MEMORY ARCHITECTURE;

EID: 84867410972     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPSW.2012.83     Document Type: Conference Paper

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