Vertical InAs nanowire MOSFETs with I DS = 1.34 mA/μm and g m = 1.19 mS/μm at V DS = 0.5 v

Device Research Conference - Conference Digest, DRC

Volumn , Issue , 2012, Pages 195-196

  Persson, Karl Magnus ^a   Berg, Martin ^a   Borg, Mattias ^a   Wu, Jun ^a   Sjöland, Henrik ^a   Lind, Erik ^a   Wernersson, Lars Erik ^a  

^a LUND UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT LEVELS; DRAIN RESISTANCES; ELECTROSTATIC CONTROL; INAS; MOSFETS; NANOWIRE MOSFETS; NARROW WIRES; ON-RESISTANCE; PERFORMANCE LIMITATIONS; SI CMOS; SI SUBSTRATES; SI-TECHNOLOGY; SINGLE NANOWIRES; SOURCE RESISTANCE; SPACER LAYER; SUBTHRESHOLD SWING; TRANSISTOR ARCHITECTURE;

CMOS INTEGRATED CIRCUITS; HAFNIUM OXIDES; MOSFET DEVICES; NANOWIRES; SILICON; WIRE;

INDIUM ARSENIDE;

EID: 84866910921     PISSN: 15483770     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DRC.2012.6256966     Document Type: Conference Paper

References (5)

1. J. A. del Alamo, Nature, vol. 479, no. 7373, pp. 317-323, Nov. 2011
2. C. Thelander et al., IEEE Electron Device Lett., vol. 29, no. 3, pp. 206-208, Mar. 2008
3. S. Gorji Ghalamestani et al., J. Crystal Growth., vol. 332, no. 1, pp. 12-16, Oct. 2011
4. A. Dey et al., IEEE Electron Device Lett., (Accepted for publication 2012)
5. S. Johansson et al., IEEE Trans. Microw. Theory Tech., vol. 59, no 10, Oct. 2011